Lines Matching defs:ad9389b_rd
110 static int ad9389b_rd(struct v4l2_subdev *sd, u8 reg)
137 ad9389b_wr(sd, reg, (ad9389b_rd(sd, reg) & clr_mask) | val_mask);
153 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT;
158 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT;
328 reg->val = ad9389b_rd(sd, reg->reg & 0xff);
372 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT) ?
374 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT) ?
378 (ad9389b_rd(sd, 0xaf) & 0x02) ?
380 (ad9389b_rd(sd, 0xa1) & 0x3c) ?
382 v4l2_info(sd, "ad9389b: %s\n", (ad9389b_rd(sd, 0xb8) & 0x40) ?
385 states[ad9389b_rd(sd, 0xc8) & 0xf],
386 errors[ad9389b_rd(sd, 0xc8) >> 4],
388 ad9389b_rd(sd, 0x94), ad9389b_rd(sd, 0x96));
389 manual_gear = ad9389b_rd(sd, 0x98) & 0x80;
391 ad9389b_rd(sd, 0x3b) & 0x01 ? "limited" : "full");
394 manual_gear ? ((ad9389b_rd(sd, 0x98) & 0x70) >> 4) :
395 ((ad9389b_rd(sd, 0x9e) & 0x0e) >> 1));
396 if (ad9389b_rd(sd, 0xaf) & 0x02) {
398 u8 manual_cts = ad9389b_rd(sd, 0x0a) & 0x80;
399 u32 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
400 ad9389b_rd(sd, 0x02) << 8 |
401 ad9389b_rd(sd, 0x03);
402 u8 vic_detect = ad9389b_rd(sd, 0x3e) >> 2;
403 u8 vic_sent = ad9389b_rd(sd, 0x3d) & 0x3f;
407 CTS = (ad9389b_rd(sd, 0x07) & 0xf) << 16 |
408 ad9389b_rd(sd, 0x08) << 8 |
409 ad9389b_rd(sd, 0x09);
411 CTS = (ad9389b_rd(sd, 0x04) & 0xf) << 16 |
412 ad9389b_rd(sd, 0x05) << 8 |
413 ad9389b_rd(sd, 0x06);
414 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
415 ad9389b_rd(sd, 0x02) << 8 |
416 ad9389b_rd(sd, 0x03);
455 if ((ad9389b_rd(sd, 0x41) & 0x40) == 0)
520 irqs_rd = ad9389b_rd(sd, 0x94);
534 irq_status = ad9389b_rd(sd, 0x96);
840 ed.segment = ad9389b_rd(sd, 0xc4);
903 u8 status = ad9389b_rd(sd, 0x42);
952 while (state->power_on && (ad9389b_rd(sd, 0x41) & 0x40)) {
1014 u8 edidRdy = ad9389b_rd(sd, 0xc5);
1022 segment = ad9389b_rd(sd, 0xc4);
1142 state->chip_revision = ad9389b_rd(sd, 0x0);
1149 ad9389b_rd(sd, 0x41), state->chip_revision);