Lines Matching defs:ves1820_writereg
47 static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data)
94 ves1820_writereg(state, 0x00, reg0 & 0xfe);
95 ves1820_writereg(state, 0x00, reg0 | 0x01);
169 ves1820_writereg(state, 0x03, NDEC);
170 ves1820_writereg(state, 0x0a, BDR & 0xff);
171 ves1820_writereg(state, 0x0b, (BDR >> 8) & 0xff);
172 ves1820_writereg(state, 0x0c, (BDR >> 16) & 0x3f);
174 ves1820_writereg(state, 0x0d, BDRI);
175 ves1820_writereg(state, 0x0e, SFIL);
185 ves1820_writereg(state, 0, 0);
188 ves1820_writereg(state, i, ves1820_inittab[i]);
190 ves1820_writereg(state, 2, ves1820_inittab[2] | 0x08);
192 ves1820_writereg(state, 0x34, state->pwm);
217 ves1820_writereg(state, 0x34, state->pwm);
219 ves1820_writereg(state, 0x01, reg0x01[real_qam]);
220 ves1820_writereg(state, 0x05, reg0x05[real_qam]);
221 ves1820_writereg(state, 0x08, reg0x08[real_qam]);
222 ves1820_writereg(state, 0x09, reg0x09[real_qam]);
225 ves1820_writereg(state, 2, ves1820_inittab[2] | (state->config->selagc ? 0x08 : 0));
297 ves1820_writereg(state, 0x10, ves1820_inittab[0x10] & 0xdf);
298 ves1820_writereg(state, 0x10, ves1820_inittab[0x10]);
339 ves1820_writereg(state, 0x1b, 0x02); /* pdown ADC */
340 ves1820_writereg(state, 0x00, 0x80); /* standby */