Lines Matching defs:state
47 static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data)
50 struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 3 };
53 ret = i2c_transfer(state->i2c, &msg, 1);
62 static u8 ves1820_readreg(struct ves1820_state *state, u8 reg)
67 {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 2},
68 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
72 ret = i2c_transfer(state->i2c, msg, 2);
81 static int ves1820_setup_reg0(struct ves1820_state *state,
84 reg0 |= state->reg0 & 0x62;
87 if (!state->config->invert) reg0 |= 0x20;
90 if (!state->config->invert) reg0 &= ~0x20;
94 ves1820_writereg(state, 0x00, reg0 & 0xfe);
95 ves1820_writereg(state, 0x00, reg0 | 0x01);
97 state->reg0 = reg0;
102 static int ves1820_set_symbolrate(struct ves1820_state *state, u32 symbolrate)
114 if (symbolrate > state->config->xin / 2)
115 symbolrate = state->config->xin / 2;
120 if (symbolrate < state->config->xin / 16)
122 if (symbolrate < state->config->xin / 32)
124 if (symbolrate < state->config->xin / 64)
128 fpxin = state->config->xin * 10ULL;
151 fin = state->config->xin >> 4;
160 BDRI = (((state->config->xin << 5) / symbolrate) + 1) / 2;
169 ves1820_writereg(state, 0x03, NDEC);
170 ves1820_writereg(state, 0x0a, BDR & 0xff);
171 ves1820_writereg(state, 0x0b, (BDR >> 8) & 0xff);
172 ves1820_writereg(state, 0x0c, (BDR >> 16) & 0x3f);
174 ves1820_writereg(state, 0x0d, BDRI);
175 ves1820_writereg(state, 0x0e, SFIL);
182 struct ves1820_state* state = fe->demodulator_priv;
185 ves1820_writereg(state, 0, 0);
188 ves1820_writereg(state, i, ves1820_inittab[i]);
189 if (state->config->selagc)
190 ves1820_writereg(state, 2, ves1820_inittab[2] | 0x08);
192 ves1820_writereg(state, 0x34, state->pwm);
200 struct ves1820_state* state = fe->demodulator_priv;
216 ves1820_set_symbolrate(state, p->symbol_rate);
217 ves1820_writereg(state, 0x34, state->pwm);
219 ves1820_writereg(state, 0x01, reg0x01[real_qam]);
220 ves1820_writereg(state, 0x05, reg0x05[real_qam]);
221 ves1820_writereg(state, 0x08, reg0x08[real_qam]);
222 ves1820_writereg(state, 0x09, reg0x09[real_qam]);
224 ves1820_setup_reg0(state, reg0x00[real_qam], p->inversion);
225 ves1820_writereg(state, 2, ves1820_inittab[2] | (state->config->selagc ? 0x08 : 0));
232 struct ves1820_state* state = fe->demodulator_priv;
236 sync = ves1820_readreg(state, 0x11);
258 struct ves1820_state* state = fe->demodulator_priv;
260 u32 _ber = ves1820_readreg(state, 0x14) |
261 (ves1820_readreg(state, 0x15) << 8) |
262 ((ves1820_readreg(state, 0x16) & 0x0f) << 16);
270 struct ves1820_state* state = fe->demodulator_priv;
272 u8 gain = ves1820_readreg(state, 0x17);
280 struct ves1820_state* state = fe->demodulator_priv;
282 u8 quality = ~ves1820_readreg(state, 0x18);
290 struct ves1820_state* state = fe->demodulator_priv;
292 *ucblocks = ves1820_readreg(state, 0x13) & 0x7f;
297 ves1820_writereg(state, 0x10, ves1820_inittab[0x10] & 0xdf);
298 ves1820_writereg(state, 0x10, ves1820_inittab[0x10]);
306 struct ves1820_state* state = fe->demodulator_priv;
310 sync = ves1820_readreg(state, 0x11);
311 afc = ves1820_readreg(state, 0x19);
318 if (!state->config->invert) {
319 p->inversion = (state->reg0 & 0x20) ? INVERSION_ON : INVERSION_OFF;
321 p->inversion = (!(state->reg0 & 0x20)) ? INVERSION_ON : INVERSION_OFF;
324 p->modulation = ((state->reg0 >> 2) & 7) + QAM_16;
337 struct ves1820_state* state = fe->demodulator_priv;
339 ves1820_writereg(state, 0x1b, 0x02); /* pdown ADC */
340 ves1820_writereg(state, 0x00, 0x80); /* standby */
356 struct ves1820_state* state = fe->demodulator_priv;
357 kfree(state);
366 struct ves1820_state* state = NULL;
368 /* allocate memory for the internal state */
369 state = kzalloc(sizeof(struct ves1820_state), GFP_KERNEL);
370 if (state == NULL)
373 /* setup the state */
374 state->reg0 = ves1820_inittab[0];
375 state->config = config;
376 state->i2c = i2c;
377 state->pwm = pwm;
380 if ((ves1820_readreg(state, 0x1a) & 0xf0) != 0x70)
384 printk("ves1820: pwm=0x%02x\n", state->pwm);
387 memcpy(&state->frontend.ops, &ves1820_ops, sizeof(struct dvb_frontend_ops));
388 state->frontend.ops.info.symbol_rate_min = (state->config->xin / 2) / 64; /* SACLK/64 == (XIN/2)/64 */
389 state->frontend.ops.info.symbol_rate_max = (state->config->xin / 2) / 4; /* SACLK/4 */
390 state->frontend.demodulator_priv = state;
392 return &state->frontend;
395 kfree(state);