Lines Matching refs:SACLK
20 #define SACLK 96000000U
118 /* setup PLL (this assumes SACLK = 96MHz) */
157 tda10086_write_byte(state, 0x34, (((1<<19) * (22000/1000)) / (SACLK/1000)));
158 tda10086_write_byte(state, 0x35, (((1<<19) * (22000/1000)) / (SACLK/1000)) >> 8);
300 if (symbol_rate < SACLK / 10000 * 137) {
303 } else if (symbol_rate < SACLK / 10000 * 208) {
306 } else if (symbol_rate < SACLK / 10000 * 270) {
309 } else if (symbol_rate < SACLK / 10000 * 416) {
312 } else if (symbol_rate < SACLK / 10000 * 550) {
315 } else if (symbol_rate < SACLK / 10000 * 833) {
318 } else if (symbol_rate < SACLK / 10000 * 1100) {
321 } else if (symbol_rate < SACLK / 10000 * 1666) {
324 } else if (symbol_rate < SACLK / 10000 * 2200) {
327 } else if (symbol_rate < SACLK / 10000 * 3333) {
338 big += ((SACLK/1000ULL)-1ULL);
339 do_div(big, (SACLK/1000ULL));
344 bdri = ((32 * (SACLK/1000)) + (tmp-1)) / tmp;
429 freqoff = ((1<<16) * freqoff) / (SACLK/1000);
468 tmp64 = (tmp64 * (SACLK/1000ULL));