Lines Matching refs:tda1004x_write_mask
160 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
201 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
210 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
365 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
397 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
398 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
399 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
487 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
491 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f);
498 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0);
546 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
613 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
616 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
617 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
618 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
619 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
620 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
621 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
624 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
625 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
628 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
644 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
651 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
655 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
659 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00); // set AGC polarities
665 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
669 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40);
670 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
672 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80);
673 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10,
677 tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on
686 // tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes
702 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
703 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
704 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
707 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
730 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
731 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */
732 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
733 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
735 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
741 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
747 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
752 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
756 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
760 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
770 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
774 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
778 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
782 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
807 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
811 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
821 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
822 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
826 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
827 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
831 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
832 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
836 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
837 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
841 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
842 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
852 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
853 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
857 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
858 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
862 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
863 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
873 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
874 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
878 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
880 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
1138 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1139 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1140 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1189 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1198 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f,
1201 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0);
1202 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);