Lines Matching refs:state
141 static int write_reg(struct stv *state, u16 reg, u8 val)
143 struct i2c_adapter *adap = state->base->i2c;
145 struct i2c_msg msg = {.addr = state->base->adr, .flags = 0,
150 state->base->adr, reg, val);
173 static int read_reg(struct stv *state, u16 reg, u8 *val)
175 return i2c_read_regs16(state->base->i2c, state->base->adr,
179 static int read_regs(struct stv *state, u16 reg, u8 *val, int len)
181 return i2c_read_regs16(state->base->i2c, state->base->adr,
185 static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val)
190 mutex_lock(&state->base->reg_lock);
191 status = read_reg(state, reg, &tmp);
193 status = write_reg(state, reg, (tmp & ~mask) | (val & mask));
194 mutex_unlock(&state->base->reg_lock);
198 static int write_field(struct stv *state, u32 field, u8 val)
203 status = read_reg(state, field >> 16, &old);
211 return write_reg(state, field >> 16, new);
215 write_field(state, state->nr ? FSTV0910_P2_##_reg : \
219 write_reg(state, state->nr ? RSTV0910_P2_##_reg : \
223 read_reg(state, state->nr ? RSTV0910_P2_##_reg : \
442 static u8 get_optim_cloop(struct stv *state,
452 if (state->symbol_rate <= 3000000)
454 else if (state->symbol_rate <= 7000000)
456 else if (state->symbol_rate <= 15000000)
458 else if (state->symbol_rate <= 25000000)
469 static int get_cur_symbol_rate(struct stv *state, u32 *p_symbol_rate)
483 if (!state->started)
486 read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3);
487 read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2);
488 read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1);
489 read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0);
490 read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2);
491 read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1);
492 read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0);
502 symbol_rate = (u32)(((u64)symbol_rate * state->base->mclk) >> 32);
510 static int get_signal_parameters(struct stv *state)
514 if (!state->started)
517 if (state->receive_mode == RCVMODE_DVBS2) {
518 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
519 state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
520 state->pilots = (tmp & 0x01) != 0;
521 state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1);
523 } else if (state->receive_mode == RCVMODE_DVBS) {
524 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
525 state->puncture_rate = FEC_NONE;
528 state->puncture_rate = FEC_1_2;
531 state->puncture_rate = FEC_2_3;
534 state->puncture_rate = FEC_3_4;
537 state->puncture_rate = FEC_5_6;
540 state->puncture_rate = FEC_7_8;
543 state->is_vcm = 0;
544 state->is_standard_broadcast = 1;
545 state->feroll_off = FE_SAT_35;
550 static int tracking_optimization(struct stv *state)
554 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp);
557 switch (state->receive_mode) {
568 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp);
570 if (state->receive_mode == RCVMODE_DVBS2) {
572 write_shared_reg(state,
573 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01,
576 if (state->fectype == DVBS2_64K) {
577 u8 aclc = get_optim_cloop(state, state->mod_cod,
578 state->pilots);
580 if (state->mod_cod <= FE_QPSK_910) {
581 write_reg(state, RSTV0910_P2_ACLC2S2Q +
582 state->regoff, aclc);
583 } else if (state->mod_cod <= FE_8PSK_910) {
584 write_reg(state, RSTV0910_P2_ACLC2S2Q +
585 state->regoff, 0x2a);
586 write_reg(state, RSTV0910_P2_ACLC2S28 +
587 state->regoff, aclc);
588 } else if (state->mod_cod <= FE_16APSK_910) {
589 write_reg(state, RSTV0910_P2_ACLC2S2Q +
590 state->regoff, 0x2a);
591 write_reg(state, RSTV0910_P2_ACLC2S216A +
592 state->regoff, aclc);
593 } else if (state->mod_cod <= FE_32APSK_910) {
594 write_reg(state, RSTV0910_P2_ACLC2S2Q +
595 state->regoff, 0x2a);
596 write_reg(state, RSTV0910_P2_ACLC2S232A +
597 state->regoff, aclc);
640 static int get_signal_to_noise(struct stv *state, s32 *signal_to_noise)
650 if (!state->started)
653 if (state->receive_mode == RCVMODE_DVBS2) {
654 read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff,
656 read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff,
661 read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff,
663 read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff,
673 static int get_bit_error_rate_s(struct stv *state, u32 *bernumerator,
678 int status = read_regs(state,
679 RSTV0910_P2_ERRCNT12 + state->regoff,
686 state->last_berdenominator = 1ULL << ((state->berscale * 2) +
688 state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) |
690 if (state->last_bernumerator < 256 && state->berscale < 6) {
691 state->berscale += 1;
692 status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
693 state->regoff,
694 0x20 | state->berscale);
695 } else if (state->last_bernumerator > 1024 &&
696 state->berscale > 2) {
697 state->berscale -= 1;
698 status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
699 state->regoff, 0x20 |
700 state->berscale);
703 *bernumerator = state->last_bernumerator;
704 *berdenominator = state->last_berdenominator;
748 static int get_bit_error_rate_s2(struct stv *state, u32 *bernumerator,
753 int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff,
760 state->last_berdenominator =
761 dvbs2_nbch((enum dvbs2_mod_cod)state->mod_cod,
762 state->fectype) <<
763 (state->berscale * 2);
764 state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) |
766 if (state->last_bernumerator < 256 && state->berscale < 6) {
767 state->berscale += 1;
768 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
769 0x20 | state->berscale);
770 } else if (state->last_bernumerator > 1024 &&
771 state->berscale > 2) {
772 state->berscale -= 1;
773 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
774 0x20 | state->berscale);
777 *bernumerator = state->last_bernumerator;
778 *berdenominator = state->last_berdenominator;
782 static int get_bit_error_rate(struct stv *state, u32 *bernumerator,
788 switch (state->receive_mode) {
790 return get_bit_error_rate_s(state,
793 return get_bit_error_rate_s2(state,
801 static int set_mclock(struct stv *state, u32 master_clock)
805 u32 quartz = state->base->extclk / 1000000;
854 write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf);
855 write_reg(state, RSTV0910_NCOARSE2, odf);
856 write_reg(state, RSTV0910_NCOARSE1, ndiv);
859 state->base->mclk = fvco / (2 * odf) * 1000000;
864 static int stop(struct stv *state)
866 if (state->started) {
869 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
870 state->tscfgh | 0x01);
871 read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp);
873 write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp);
875 write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B);
877 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c);
878 state->started = 0;
880 state->receive_mode = RCVMODE_NONE;
884 static void set_pls(struct stv *state, u32 pls_code)
886 if (pls_code == state->cur_scrambling_code)
890 write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff,
892 write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff,
894 write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff,
896 state->cur_scrambling_code = pls_code;
899 static void set_isi(struct stv *state, u32 isi)
908 write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff,
910 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff);
916 static void set_stream_modes(struct stv *state,
919 set_isi(state, p->stream_id);
920 set_pls(state, p->scrambling_sequence_index);
923 static int init_search_param(struct stv *state,
937 set_stream_modes(state, p);
941 static int enable_puncture_rate(struct stv *state, enum fe_code_rate rate)
967 return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val);
970 static int set_vth_default(struct stv *state)
972 state->vth[0] = 0xd7;
973 state->vth[1] = 0x85;
974 state->vth[2] = 0x58;
975 state->vth[3] = 0x3a;
976 state->vth[4] = 0x34;
977 state->vth[5] = 0x28;
978 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
979 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
980 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
981 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
982 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
983 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
987 static int set_vth(struct stv *state)
999 int status = read_regs(state,
1000 RSTV0910_P2_NNOSDATAT1 + state->regoff,
1007 if (state->vth[i] > vth)
1008 state->vth[i] = vth;
1010 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
1011 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
1012 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
1013 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
1014 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
1015 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
1019 static int start(struct stv *state, struct dtv_frontend_properties *p)
1028 state->receive_mode = RCVMODE_NONE;
1029 state->demod_lock_time = 0;
1032 if (state->started)
1033 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C);
1035 init_search_param(state, p);
1038 state->demod_timeout = 3000;
1039 state->fec_timeout = 2000;
1041 state->demod_timeout = 2500;
1042 state->fec_timeout = 1300;
1044 state->demod_timeout = 1000;
1045 state->fec_timeout = 650;
1047 state->demod_timeout = 700;
1048 state->fec_timeout = 350;
1050 state->demod_timeout = 400;
1051 state->fec_timeout = 200;
1053 state->demod_timeout = 300;
1054 state->fec_timeout = 200;
1058 symb = muldiv32(p->symbol_rate, 65536, state->base->mclk);
1059 write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff,
1061 write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF));
1063 state->demod_bits |= 0x80;
1064 write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits);
1067 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ®_dmdcfgmd);
1068 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff,
1071 write_shared_reg(state,
1072 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00);
1075 write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00);
1076 write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F);
1078 enable_puncture_rate(state, FEC_NONE);
1081 write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B);
1082 write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A);
1083 write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84);
1084 write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84);
1085 write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C);
1086 write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79);
1088 write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29);
1089 write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09);
1090 write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84);
1091 write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84);
1097 write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08);
1098 write_reg(state, RSTV0910_TSTRES0, 0);
1100 set_vth_default(state);
1102 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1104 write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46);
1107 freq = (state->search_range / 2000) + 80;
1109 freq = (state->search_range / 2000) + 1600;
1110 freq = (freq << 16) / (state->base->mclk / 1000);
1112 write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff,
1114 write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff));
1117 write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff,
1119 write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff));
1122 write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0);
1123 write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0);
1125 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1127 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15);
1129 state->demod_lock_time += TUNING_DELAY;
1130 state->started = 1;
1135 static int init_diseqc(struct stv *state)
1137 u16 offs = state->nr ? 0x40 : 0; /* Address offset */
1138 u8 freq = ((state->base->mclk + 11000 * 32) / (22000 * 32));
1141 write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00);
1142 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */
1143 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */
1144 write_reg(state, RSTV0910_P1_DISTXF22 + offs, freq);
1148 static int probe(struct stv *state)
1152 state->receive_mode = RCVMODE_NONE;
1153 state->started = 0;
1155 if (read_reg(state, RSTV0910_MID, &id) < 0)
1162 write_reg(state, RSTV0910_P1_I2CRPT, 0x24);
1164 write_reg(state, RSTV0910_P2_I2CRPT, 0x24);
1166 write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */
1168 write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */
1169 write_reg(state, RSTV0910_PADCFG, 0x05); /* RFAGC Pads Dev = 05 */
1170 write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */
1171 write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */
1172 write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */
1174 if (state->single)
1175 write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */
1177 write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */
1179 write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */
1180 write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */
1182 write_reg(state, RSTV0910_P1_CAR3CFG, 0x02);
1183 write_reg(state, RSTV0910_P2_CAR3CFG, 0x02);
1184 write_reg(state, RSTV0910_P1_DMDCFG4, 0x04);
1185 write_reg(state, RSTV0910_P2_DMDCFG4, 0x04);
1187 write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */
1188 write_reg(state, RSTV0910_TSTRES0, 0x00);
1190 write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00);
1191 write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00);
1193 write_reg(state, RSTV0910_P1_TMGCFG2, 0x80);
1194 write_reg(state, RSTV0910_P2_TMGCFG2, 0x80);
1196 set_mclock(state, 135000000);
1199 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1200 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1201 write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */
1202 write_reg(state, RSTV0910_P1_TSCFGL, 0x20);
1204 write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed);
1206 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1207 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1208 write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */
1209 write_reg(state, RSTV0910_P2_TSCFGL, 0x20);
1211 write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed);
1214 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1215 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1216 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1217 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1219 write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt);
1220 write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt);
1222 write_reg(state, RSTV0910_P1_TSINSDELM, 0x17);
1223 write_reg(state, RSTV0910_P1_TSINSDELL, 0xff);
1225 write_reg(state, RSTV0910_P2_TSINSDELM, 0x17);
1226 write_reg(state, RSTV0910_P2_TSINSDELL, 0xff);
1228 init_diseqc(state);
1234 struct stv *state = fe->demodulator_priv;
1235 u8 i2crpt = state->i2crpt & ~0x86;
1248 mutex_lock(&state->base->i2c_lock);
1254 if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT :
1257 if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
1258 mutex_unlock(&state->base->i2c_lock);
1259 dev_err(&state->base->i2c->dev,
1265 state->i2crpt = i2crpt;
1268 if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
1269 mutex_unlock(&state->base->i2c_lock);
1275 struct stv *state = fe->demodulator_priv;
1277 state->base->count--;
1278 if (state->base->count == 0) {
1279 list_del(&state->base->stvlist);
1280 kfree(state->base);
1282 kfree(state);
1288 struct stv *state = fe->demodulator_priv;
1291 stop(state);
1294 state->symbol_rate = p->symbol_rate;
1295 stat = start(state, p);
1299 static int manage_matype_info(struct stv *state)
1301 if (!state->started)
1303 if (state->receive_mode == RCVMODE_DVBS2) {
1306 read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff,
1308 state->feroll_off =
1310 state->is_vcm = (bbheader[0] & 0x10) == 0;
1311 state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0;
1312 } else if (state->receive_mode == RCVMODE_DVBS) {
1313 state->is_vcm = 0;
1314 state->is_standard_broadcast = 1;
1315 state->feroll_off = FE_SAT_35;
1322 struct stv *state = fe->demodulator_priv;
1326 if (!get_signal_to_noise(state, &snrval)) {
1338 struct stv *state = fe->demodulator_priv;
1342 get_bit_error_rate(state, &n, &d);
1354 struct stv *state = fe->demodulator_priv;
1355 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
1361 read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2);
1366 read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2);
1381 struct stv *state = fe->demodulator_priv;
1390 read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state);
1393 read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus);
1399 set_vth(state);
1415 if (state->receive_mode == RCVMODE_NONE) {
1416 state->receive_mode = cur_receive_mode;
1417 state->demod_lock_time = jiffies;
1418 state->first_time_lock = 1;
1420 get_signal_parameters(state);
1421 tracking_optimization(state);
1423 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1424 state->tscfgh);
1426 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1427 state->tscfgh | 0x01);
1428 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1429 state->tscfgh);
1432 if (state->receive_mode == RCVMODE_DVBS2) {
1435 read_reg(state,
1436 RSTV0910_P2_PDELSTATUS1 + state->regoff,
1442 read_reg(state,
1443 RSTV0910_P2_VSTATUSVIT + state->regoff,
1452 if (state->first_time_lock) {
1455 state->first_time_lock = 0;
1457 manage_matype_info(state);
1459 if (state->receive_mode == RCVMODE_DVBS2) {
1464 state->demod_bits &= ~0x84;
1465 write_reg(state,
1466 RSTV0910_P2_DEMOD + state->regoff,
1467 state->demod_bits);
1468 read_reg(state,
1469 RSTV0910_P2_PDELCTRL2 + state->regoff,
1473 write_reg(state,
1474 RSTV0910_P2_PDELCTRL2 + state->regoff,
1478 write_reg(state,
1479 RSTV0910_P2_PDELCTRL2 + state->regoff,
1482 state->berscale = 2;
1483 state->last_bernumerator = 0;
1484 state->last_berdenominator = 1;
1486 write_reg(state,
1487 RSTV0910_P2_ERRCTRL1 + state->regoff,
1488 BER_SRC_S2 | state->berscale);
1490 state->berscale = 2;
1491 state->last_bernumerator = 0;
1492 state->last_berdenominator = 1;
1494 write_reg(state,
1495 RSTV0910_P2_ERRCTRL1 + state->regoff,
1496 BER_SRC_S | state->berscale);
1499 write_reg(state,
1500 RSTV0910_P2_FBERCPT4 + state->regoff, 0x00);
1505 write_reg(state,
1506 RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1);
1508 set_vth_default(state);
1509 if (state->receive_mode == RCVMODE_DVBS)
1510 enable_puncture_rate(state,
1511 state->puncture_rate);
1515 if (state->is_vcm) {
1519 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff,
1523 if (mod_cod > state->mod_cod)
1524 state->mod_cod = mod_cod;
1553 struct stv *state = fe->demodulator_priv;
1557 if (state->receive_mode == RCVMODE_DVBS2) {
1579 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
1584 } else if (state->receive_mode == RCVMODE_DVBS) {
1585 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
1609 if (state->receive_mode != RCVMODE_NONE) {
1610 get_cur_symbol_rate(state, &symbolrate);
1620 struct stv *state = fe->demodulator_priv;
1627 state->tune_time = jiffies;
1648 struct stv *state = fe->demodulator_priv;
1649 u16 offs = state->nr ? 0x40 : 0;
1653 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38);
1655 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a);
1662 static int wait_dis(struct stv *state, u8 flag, u8 val)
1666 u16 offs = state->nr ? 0x40 : 0;
1669 read_reg(state, RSTV0910_P1_DISTXSTATUS + offs, &stat);
1680 struct stv *state = fe->demodulator_priv;
1686 wait_dis(state, 0x40, 0x00);
1690 wait_dis(state, 0x20, 0x20);
1696 struct stv *state = fe->demodulator_priv;
1708 wait_dis(state, 0x40, 0x00);
1711 wait_dis(state, 0x20, 0x20);
1718 struct stv *state = fe->demodulator_priv;
1720 stop(state);
1762 static void stv0910_init_stats(struct stv *state)
1764 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
1780 struct stv *state;
1783 state = kzalloc(sizeof(*state), GFP_KERNEL);
1784 if (!state)
1787 state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40);
1788 state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00;
1789 state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4);
1791 state->tsspeed = (cfg->tsspeed ? cfg->tsspeed : 0x28);
1792 state->nr = nr;
1793 state->regoff = state->nr ? 0 : 0x200;
1794 state->search_range = 16000000;
1795 state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */
1796 state->receive_mode = RCVMODE_NONE;
1797 state->cur_scrambling_code = (~0U);
1798 state->single = cfg->single ? 1 : 0;
1803 state->base = base;
1815 state->base = base;
1816 if (probe(state) < 0) {
1824 state->fe.ops = stv0910_ops;
1825 state->fe.demodulator_priv = state;
1826 state->nr = nr;
1829 state->fe.ops.info.name, cfg->adr, dev_name(&i2c->dev));
1831 stv0910_init_stats(state);
1833 return &state->fe;
1836 kfree(state);