Lines Matching defs:stv090x_write_reg
744 static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
1206 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1215 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
3935 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3940 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
3959 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
3970 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
3978 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
3983 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
4002 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4013 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4026 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
4057 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
4065 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4070 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
4081 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4090 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4098 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4103 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
4114 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4123 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4167 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
4174 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4177 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4224 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
4227 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
4233 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4236 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4281 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
4311 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4316 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
4320 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4324 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4326 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4328 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4341 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4347 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
4361 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
4366 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
4369 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4373 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4375 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4377 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4390 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4395 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
4408 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4417 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4426 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4435 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4449 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4458 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4467 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4476 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4510 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4512 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4542 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4544 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
4550 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4553 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4558 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4561 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4578 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4584 stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c);
4591 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
4597 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4607 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4615 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4623 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4631 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4665 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4667 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4673 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4676 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4708 if (stv090x_write_reg(state, STV090x_SYNTCTRL,
4792 if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
4795 if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
4801 if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
4804 if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
4809 if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
4812 if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
4815 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
4818 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
4820 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
4827 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
4833 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4839 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
4858 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4865 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4868 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
4870 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
4889 return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg);