Lines Matching refs:intp
24 int stv0900_check_signal_presence(struct stv0900_internal *intp,
33 carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
34 | stv0900_read_reg(intp, CFR1);
36 agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
37 | stv0900_read_reg(intp, AGC2I0);
38 max_carrier = intp->srch_range[demod] / 1000;
42 max_carrier /= intp->mclk / 1000;
54 static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
63 srate = intp->symbol_rate[demod];
64 max_carrier = intp->srch_range[demod] / 1000;
66 standard = intp->srch_standard[demod];
69 max_carrier /= intp->mclk / 1000;
75 freq_inc /= intp->mclk >> 10;
121 static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
131 max_carrier = intp->srch_range[demod] / 1000;
135 max_carrier /= intp->mclk / 1000;
148 stv0900_write_reg(intp, DMDISTATE, 0x1c);
149 stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
150 stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
151 stv0900_write_reg(intp, DMDISTATE, 0x18);
152 stv0900_write_bits(intp, ALGOSWRST, 1);
154 if (intp->chip_id == 0x12) {
155 stv0900_write_bits(intp, RST_HWARE, 1);
156 stv0900_write_bits(intp, RST_HWARE, 0);
168 lock = stv0900_get_demod_lock(intp, demod, Timeout);
169 no_signal = stv0900_check_signal_presence(intp, demod);
177 stv0900_write_bits(intp, ALGOSWRST, 0);
182 static int stv0900_sw_algo(struct stv0900_internal *intp,
194 stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
196 switch (intp->srch_standard[demod]) {
199 if (intp->chip_id >= 0x20)
200 stv0900_write_reg(intp, CARFREQ, 0x3b);
202 stv0900_write_reg(intp, CARFREQ, 0xef);
204 stv0900_write_reg(intp, DMDCFGMD, 0x49);
208 if (intp->chip_id >= 0x20)
209 stv0900_write_reg(intp, CORRELABS, 0x79);
211 stv0900_write_reg(intp, CORRELABS, 0x68);
213 stv0900_write_reg(intp, DMDCFGMD, 0x89);
219 if (intp->chip_id >= 0x20) {
220 stv0900_write_reg(intp, CARFREQ, 0x3b);
221 stv0900_write_reg(intp, CORRELABS, 0x79);
223 stv0900_write_reg(intp, CARFREQ, 0xef);
224 stv0900_write_reg(intp, CORRELABS, 0x68);
227 stv0900_write_reg(intp, DMDCFGMD, 0xc9);
234 lock = stv0900_search_carr_sw_loop(intp,
240 no_signal = stv0900_check_signal_presence(intp, demod);
246 if (intp->chip_id >= 0x20) {
247 stv0900_write_reg(intp, CARFREQ, 0x49);
248 stv0900_write_reg(intp, CORRELABS, 0x9e);
250 stv0900_write_reg(intp, CARFREQ, 0xed);
251 stv0900_write_reg(intp, CORRELABS, 0x88);
254 if ((stv0900_get_bits(intp, HEADER_MODE) ==
258 s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
262 s2fw = stv0900_get_bits(intp,
270 if (intp->chip_id >= 0x20)
271 stv0900_write_reg(intp,
275 stv0900_write_reg(intp,
279 stv0900_write_reg(intp,
294 static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
300 srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
301 (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
302 (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
303 (stv0900_get_bits(intp, SYMB_FREQ0));
305 srate, stv0900_get_bits(intp, SYMB_FREQ0),
306 stv0900_get_bits(intp, SYMB_FREQ1),
307 stv0900_get_bits(intp, SYMB_FREQ2),
308 stv0900_get_bits(intp, SYMB_FREQ3));
322 static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
342 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
343 stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
346 static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
366 stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
367 stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
369 stv0900_write_reg(intp, SFRUP1, 0x7f);
370 stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
374 static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
394 stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
395 stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
398 static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
405 timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
406 (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
407 (stv0900_read_reg(intp, TMGREG2 + 2));
421 static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
426 if (intp->chip_id == 0x10) {
427 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
428 rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
429 stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
430 } else if (intp->chip_id <= 0x20)
431 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
433 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
456 static int stv0900_check_timing_lock(struct stv0900_internal *intp,
466 car_freq = stv0900_read_reg(intp, CARFREQ);
467 tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
468 tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
469 stv0900_write_reg(intp, TMGTHRISE, 0x20);
470 stv0900_write_reg(intp, TMGTHFALL, 0x0);
471 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
472 stv0900_write_reg(intp, RTC, 0x80);
473 stv0900_write_reg(intp, RTCS2, 0x40);
474 stv0900_write_reg(intp, CARFREQ, 0x0);
475 stv0900_write_reg(intp, CFRINIT1, 0x0);
476 stv0900_write_reg(intp, CFRINIT0, 0x0);
477 stv0900_write_reg(intp, AGC2REF, 0x65);
478 stv0900_write_reg(intp, DMDISTATE, 0x18);
482 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
491 stv0900_write_reg(intp, AGC2REF, 0x38);
492 stv0900_write_reg(intp, RTC, 0x88);
493 stv0900_write_reg(intp, RTCS2, 0x68);
494 stv0900_write_reg(intp, CARFREQ, car_freq);
495 stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
496 stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
505 struct stv0900_internal *intp = state->internal;
520 srate = intp->symbol_rate[d];
521 search_range = intp->srch_range[d];
528 lock = stv0900_get_demod_lock(intp, d, locktimeout);
534 if (stv0900_check_timing_lock(intp, d) == TRUE) {
535 stv0900_write_reg(intp, DMDISTATE, 0x1f);
536 stv0900_write_reg(intp, DMDISTATE, 0x15);
537 lock = stv0900_get_demod_lock(intp, d, demod_timeout);
544 if (intp->chip_id <= 0x20) {
581 if (intp->chip_id <= 0x20) {
582 tuner_freq = intp->freq[d];
583 intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
584 intp->rolloff) + intp->symbol_rate[d];
594 if (intp->chip_id <= 0x20) {
595 if (intp->tuner_type[d] == 3)
596 stv0900_set_tuner_auto(intp, tuner_freq,
597 intp->bw[d], demod);
599 stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
601 stv0900_write_reg(intp, DMDISTATE, 0x1c);
602 stv0900_write_reg(intp, CFRINIT1, 0);
603 stv0900_write_reg(intp, CFRINIT0, 0);
604 stv0900_write_reg(intp, DMDISTATE, 0x1f);
605 stv0900_write_reg(intp, DMDISTATE, 0x15);
607 stv0900_write_reg(intp, DMDISTATE, 0x1c);
608 freq = (tuner_freq * 65536) / (intp->mclk / 1000);
609 stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
610 stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
611 stv0900_write_reg(intp, DMDISTATE, 0x1f);
612 stv0900_write_reg(intp, DMDISTATE, 0x05);
615 lock = stv0900_get_demod_lock(intp, d, timeout);
672 static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
680 stv0900_write_reg(intp, vth_reg++, 0xd0);
681 stv0900_write_reg(intp, vth_reg++, 0x7d);
682 stv0900_write_reg(intp, vth_reg++, 0x53);
683 stv0900_write_reg(intp, vth_reg++, 0x2f);
684 stv0900_write_reg(intp, vth_reg++, 0x24);
685 stv0900_write_reg(intp, vth_reg++, 0x1f);
688 static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
698 stv0900_write_reg(intp, FECM, 0x10);
699 stv0900_write_reg(intp, PRVIT, 0x3f);
703 stv0900_write_reg(intp, FECM, 0x00);
707 stv0900_write_reg(intp, PRVIT, 0x2f);
710 stv0900_write_reg(intp, PRVIT, 0x01);
713 stv0900_write_reg(intp, PRVIT, 0x02);
716 stv0900_write_reg(intp, PRVIT, 0x04);
719 stv0900_write_reg(intp, PRVIT, 0x08);
722 stv0900_write_reg(intp, PRVIT, 0x20);
729 stv0900_write_reg(intp, FECM, 0x80);
733 stv0900_write_reg(intp, PRVIT, 0x13);
736 stv0900_write_reg(intp, PRVIT, 0x01);
739 stv0900_write_reg(intp, PRVIT, 0x02);
742 stv0900_write_reg(intp, PRVIT, 0x10);
751 static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
755 s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
784 static void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
788 if (intp->chip_id >= 0x30) {
790 stv0900_write_reg(intp, ACLC, 0x2b);
791 stv0900_write_reg(intp, BCLC, 0x1a);
793 stv0900_write_reg(intp, ACLC, 0x0c);
794 stv0900_write_reg(intp, BCLC, 0x1b);
796 stv0900_write_reg(intp, ACLC, 0x2c);
797 stv0900_write_reg(intp, BCLC, 0x1c);
801 stv0900_write_reg(intp, ACLC, 0x1a);
802 stv0900_write_reg(intp, BCLC, 0x09);
810 struct stv0900_internal *intp = state->internal;
828 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
829 srate += stv0900_get_timing_offst(intp, srate, demod);
831 switch (intp->result[demod].standard) {
835 if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
836 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
837 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
840 stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
841 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
843 if (intp->chip_id < 0x30) {
844 stv0900_write_reg(intp, ERRCTRL1, 0x75);
848 if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
849 stv0900_write_reg(intp, GAUSSR0, 0x98);
850 stv0900_write_reg(intp, CCIR0, 0x18);
852 stv0900_write_reg(intp, GAUSSR0, 0x18);
853 stv0900_write_reg(intp, CCIR0, 0x18);
856 stv0900_write_reg(intp, ERRCTRL1, 0x75);
860 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
861 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
862 stv0900_write_reg(intp, ACLC, 0);
863 stv0900_write_reg(intp, BCLC, 0);
864 if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
865 foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
866 pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
870 intp->chip_id);
872 stv0900_write_reg(intp, ACLC2S2Q, aclc);
874 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
875 stv0900_write_reg(intp, ACLC2S28, aclc);
878 if ((intp->demod_mode == STV0900_SINGLE) &&
881 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
882 stv0900_write_reg(intp, ACLC2S216A,
885 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
886 stv0900_write_reg(intp, ACLC2S232A,
892 modulation = intp->result[demod].modulation;
894 modulation, intp->chip_id);
896 stv0900_write_reg(intp, ACLC2S2Q, aclc);
898 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
899 stv0900_write_reg(intp, ACLC2S28, aclc);
901 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
902 stv0900_write_reg(intp, ACLC2S216A, aclc);
904 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
905 stv0900_write_reg(intp, ACLC2S232A, aclc);
910 if (intp->chip_id <= 0x11) {
911 if (intp->demod_mode != STV0900_SINGLE)
912 stv0900_activate_s2_modcod(intp, demod);
916 stv0900_write_reg(intp, ERRCTRL1, 0x67);
921 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
922 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
926 freq1 = stv0900_read_reg(intp, CFR2);
927 freq0 = stv0900_read_reg(intp, CFR1);
928 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
929 stv0900_write_reg(intp, SFRSTEP, 0x00);
930 stv0900_write_bits(intp, SCAN_ENABLE, 0);
931 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
932 stv0900_write_reg(intp, TMGCFG2, 0xc1);
933 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
935 if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
936 stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
940 if (intp->chip_id >= 0x20) {
941 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
942 (intp->srch_standard[demod] ==
944 (intp->srch_standard[demod] ==
946 stv0900_write_reg(intp, VAVSRVIT, 0x0a);
947 stv0900_write_reg(intp, VITSCALE, 0x0);
951 if (intp->chip_id < 0x20)
952 stv0900_write_reg(intp, CARHDR, 0x08);
954 if (intp->chip_id == 0x10)
955 stv0900_write_reg(intp, CORRELEXP, 0x0a);
957 stv0900_write_reg(intp, AGC2REF, 0x38);
959 if ((intp->chip_id >= 0x20) ||
961 (intp->symbol_rate[demod] < 10000000)) {
962 stv0900_write_reg(intp, CFRINIT1, freq1);
963 stv0900_write_reg(intp, CFRINIT0, freq0);
964 intp->bw[demod] = stv0900_carrier_width(srate,
965 intp->rolloff) + 10000000;
967 if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
968 if (intp->srch_algo[demod] != STV0900_WARM_START) {
969 if (intp->tuner_type[demod] == 3)
970 stv0900_set_tuner_auto(intp,
971 intp->freq[demod],
972 intp->bw[demod],
976 intp->bw[demod]);
980 if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
981 (intp->symbol_rate[demod] < 10000000))
989 if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
990 stv0900_write_reg(intp, DMDISTATE, 0x1f);
991 stv0900_write_reg(intp, CFRINIT1, freq1);
992 stv0900_write_reg(intp, CFRINIT0, freq0);
993 stv0900_write_reg(intp, DMDISTATE, 0x18);
995 while ((stv0900_get_demod_lock(intp,
999 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1000 stv0900_write_reg(intp, CFRINIT1, freq1);
1001 stv0900_write_reg(intp, CFRINIT0, freq0);
1002 stv0900_write_reg(intp, DMDISTATE, 0x18);
1009 if (intp->chip_id >= 0x20)
1010 stv0900_write_reg(intp, CARFREQ, 0x49);
1012 if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
1013 (intp->result[demod].standard == STV0900_DSS_STANDARD))
1014 stv0900_set_viterbi_tracq(intp, demod);
1018 static int stv0900_get_fec_lock(struct stv0900_internal *intp,
1027 dmd_state = stv0900_get_bits(intp, HEADER_MODE);
1037 lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
1040 lock = stv0900_get_bits(intp, LOCKEDVIT);
1058 static int stv0900_wait_for_lock(struct stv0900_internal *intp,
1067 lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
1070 lock = stv0900_get_fec_lock(intp, demod, fec_timeout);
1079 lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
1100 struct stv0900_internal *intp = state->internal;
1103 int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
1110 if (stv0900_get_bits(intp, DSS_DVB) == 1)
1125 static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
1134 derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
1135 (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
1136 (stv0900_get_bits(intp, CAR_FREQ0));
1174 struct stv0900_internal *intp = state->internal;
1177 struct stv0900_signal_info *result = &intp->result[demod];
1186 if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
1187 timing = stv0900_read_reg(intp, TMGREG2);
1189 stv0900_write_reg(intp, SFRSTEP, 0x5c);
1192 timing = stv0900_read_reg(intp, TMGREG2);
1199 if (intp->tuner_type[demod] == 3)
1200 result->frequency = stv0900_get_freq_auto(intp, d);
1204 offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
1206 result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
1207 srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
1209 result->fec = stv0900_get_vit_fec(intp, d);
1210 result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
1211 result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
1212 result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
1213 result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
1219 result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
1233 result->spectrum = stv0900_get_bits(intp, IQINV);
1240 if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
1241 (intp->symbol_rate[d] < 10000000)) {
1242 offsetFreq = result->frequency - intp->freq[d];
1243 if (intp->tuner_type[demod] == 3)
1244 intp->freq[d] = stv0900_get_freq_auto(intp, d);
1246 intp->freq[d] = stv0900_get_tuner_freq(fe);
1248 if (abs(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1255 } else if (abs(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1267 struct stv0900_internal *intp = state->internal;
1277 intp->result[demod].locked = FALSE;
1279 if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
1280 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1281 srate += stv0900_get_timing_offst(intp, srate, demod);
1282 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
1283 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
1287 freq1 = stv0900_read_reg(intp, CFR2);
1288 freq0 = stv0900_read_reg(intp, CFR1);
1289 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1290 stv0900_write_bits(intp, SPECINV_CONTROL,
1292 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1293 stv0900_write_reg(intp, CFRINIT1, freq1);
1294 stv0900_write_reg(intp, CFRINIT0, freq0);
1295 stv0900_write_reg(intp, DMDISTATE, 0x18);
1296 if (stv0900_wait_for_lock(intp, demod,
1298 intp->result[demod].locked = TRUE;
1302 stv0900_write_bits(intp, SPECINV_CONTROL,
1304 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1305 stv0900_write_reg(intp, CFRINIT1, freq1);
1306 stv0900_write_reg(intp, CFRINIT0, freq0);
1307 stv0900_write_reg(intp, DMDISTATE, 0x18);
1308 if (stv0900_wait_for_lock(intp, demod,
1310 intp->result[demod].locked = TRUE;
1318 intp->result[demod].locked = FALSE;
1323 static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
1334 stv0900_write_reg(intp, AGC2REF, 0x38);
1335 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1336 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1338 stv0900_write_bits(intp, AUTO_GUP, 1);
1339 stv0900_write_bits(intp, AUTO_GLOW, 1);
1341 stv0900_write_reg(intp, DMDT0M, 0x0);
1343 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1344 nb_steps = -1 + (intp->srch_range[demod] / 1000000);
1353 freq_step = (1000000 << 8) / (intp->mclk >> 8);
1364 stv0900_write_reg(intp, DMDISTATE, 0x5C);
1365 stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
1366 stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff);
1367 stv0900_write_reg(intp, DMDISTATE, 0x58);
1372 agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
1373 | stv0900_read_reg(intp, AGC2I0);
1388 struct stv0900_internal *intp = state->internal;
1401 if (intp->chip_id >= 0x30)
1406 stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
1407 stv0900_write_reg(intp, TMGCFG, 0x12);
1408 stv0900_write_reg(intp, TMGTHRISE, 0xf0);
1409 stv0900_write_reg(intp, TMGTHFALL, 0xe0);
1410 stv0900_write_bits(intp, SCAN_ENABLE, 1);
1411 stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
1412 stv0900_write_reg(intp, SFRUP1, 0x83);
1413 stv0900_write_reg(intp, SFRUP0, 0xc0);
1414 stv0900_write_reg(intp, SFRLOW1, 0x82);
1415 stv0900_write_reg(intp, SFRLOW0, 0xa0);
1416 stv0900_write_reg(intp, DMDT0M, 0x0);
1417 stv0900_write_reg(intp, AGC2REF, 0x50);
1419 if (intp->chip_id >= 0x30) {
1420 stv0900_write_reg(intp, CARFREQ, 0x99);
1421 stv0900_write_reg(intp, SFRSTEP, 0x98);
1422 } else if (intp->chip_id >= 0x20) {
1423 stv0900_write_reg(intp, CARFREQ, 0x6a);
1424 stv0900_write_reg(intp, SFRSTEP, 0x95);
1426 stv0900_write_reg(intp, CARFREQ, 0xed);
1427 stv0900_write_reg(intp, SFRSTEP, 0x73);
1430 if (intp->symbol_rate[demod] <= 2000000)
1432 else if (intp->symbol_rate[demod] <= 5000000)
1434 else if (intp->symbol_rate[demod] <= 12000000)
1439 nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
1447 currier_step = (intp->srch_range[demod] / 1000) / 10;
1453 tuner_freq = intp->freq[demod];
1456 stv0900_write_reg(intp, DMDISTATE, 0x5f);
1457 stv0900_write_bits(intp, DEMOD_MODE, 0);
1462 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
1465 agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
1466 stv0900_read_reg(intp, AGC2I0);
1470 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1488 if (intp->tuner_type[demod] == 3)
1489 stv0900_set_tuner_auto(intp, tuner_freq,
1490 intp->bw[demod], demod);
1493 intp->bw[demod]);
1500 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1508 struct stv0900_internal *intp = state->internal;
1517 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1522 symbmax /= (intp->mclk / 1000);
1526 symbmin /= (intp->mclk / 1000);
1529 symb /= (intp->mclk / 1000);
1533 symbmax /= (intp->mclk / 100);
1537 symbmin /= (intp->mclk / 100);
1540 symb /= (intp->mclk / 100);
1544 coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
1545 | stv0900_read_reg(intp, CFR1);
1547 if (symbcomp < intp->symbol_rate[demod])
1550 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1551 stv0900_write_reg(intp, TMGCFG2, 0xc1);
1552 stv0900_write_reg(intp, TMGTHRISE, 0x20);
1553 stv0900_write_reg(intp, TMGTHFALL, 0x00);
1554 stv0900_write_reg(intp, TMGCFG, 0xd2);
1555 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1556 stv0900_write_reg(intp, AGC2REF, 0x38);
1558 if (intp->chip_id >= 0x30)
1559 stv0900_write_reg(intp, CARFREQ, 0x79);
1560 else if (intp->chip_id >= 0x20)
1561 stv0900_write_reg(intp, CARFREQ, 0x49);
1563 stv0900_write_reg(intp, CARFREQ, 0xed);
1565 stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
1566 stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
1568 stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
1569 stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
1571 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
1572 stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
1574 stv0900_write_reg(intp, DMDT0M, 0x20);
1575 stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
1576 stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff);
1577 stv0900_write_reg(intp, DMDISTATE, 0x15);
1586 struct stv0900_internal *intp = state->internal;
1605 if (intp->chip_id < 0x20) {
1613 if (intp->chip_id <= 0x20)
1618 agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
1624 if (intp->chip_id == 0x10)
1625 stv0900_write_reg(intp, CORRELEXP, 0xaa);
1627 if (intp->chip_id < 0x20)
1628 stv0900_write_reg(intp, CARHDR, 0x55);
1630 stv0900_write_reg(intp, CARHDR, 0x20);
1632 if (intp->chip_id <= 0x20)
1633 stv0900_write_reg(intp, CARCFG, 0xc4);
1635 stv0900_write_reg(intp, CARCFG, 0x6);
1637 stv0900_write_reg(intp, RTCS2, 0x44);
1639 if (intp->chip_id >= 0x20) {
1640 stv0900_write_reg(intp, EQUALCFG, 0x41);
1641 stv0900_write_reg(intp, FFECFG, 0x41);
1642 stv0900_write_reg(intp, VITSCALE, 0x82);
1643 stv0900_write_reg(intp, VAVSRVIT, 0x0);
1649 stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
1658 lock = stv0900_get_demod_lock(intp,
1668 agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
1669 | stv0900_read_reg(intp, AGC2I0);
1674 dstatus2 = stv0900_read_reg(intp, DSTATUS2);
1694 static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
1701 stv0900_write_reg(intp, vth_reg++, 0x96);
1702 stv0900_write_reg(intp, vth_reg++, 0x64);
1703 stv0900_write_reg(intp, vth_reg++, 0x36);
1704 stv0900_write_reg(intp, vth_reg++, 0x23);
1705 stv0900_write_reg(intp, vth_reg++, 0x1e);
1706 stv0900_write_reg(intp, vth_reg++, 0x19);
1709 static void stv0900_set_search_standard(struct stv0900_internal *intp,
1715 switch (intp->srch_standard[demod]) {
1731 switch (intp->srch_standard[demod]) {
1734 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1735 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
1736 stv0900_write_bits(intp, STOP_CLKVIT, 0);
1737 stv0900_set_dvbs1_track_car_loop(intp,
1739 intp->symbol_rate[demod]);
1740 stv0900_write_reg(intp, CAR2CFG, 0x22);
1742 stv0900_set_viterbi_acq(intp, demod);
1743 stv0900_set_viterbi_standard(intp,
1744 intp->srch_standard[demod],
1745 intp->fec[demod], demod);
1749 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
1750 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1751 stv0900_write_bits(intp, STOP_CLKVIT, 1);
1752 stv0900_write_reg(intp, ACLC, 0x1a);
1753 stv0900_write_reg(intp, BCLC, 0x09);
1754 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1755 stv0900_write_reg(intp, CAR2CFG, 0x26);
1757 stv0900_write_reg(intp, CAR2CFG, 0x66);
1759 if (intp->demod_mode != STV0900_SINGLE) {
1760 if (intp->chip_id <= 0x11)
1761 stv0900_stop_all_s2_modcod(intp, demod);
1763 stv0900_activate_s2_modcod(intp, demod);
1766 stv0900_activate_s2_modcod_single(intp, demod);
1768 stv0900_set_viterbi_tracq(intp, demod);
1773 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1774 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1775 stv0900_write_bits(intp, STOP_CLKVIT, 0);
1776 stv0900_write_reg(intp, ACLC, 0x1a);
1777 stv0900_write_reg(intp, BCLC, 0x09);
1778 stv0900_set_dvbs1_track_car_loop(intp,
1780 intp->symbol_rate[demod]);
1781 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1782 stv0900_write_reg(intp, CAR2CFG, 0x26);
1784 stv0900_write_reg(intp, CAR2CFG, 0x66);
1786 if (intp->demod_mode != STV0900_SINGLE) {
1787 if (intp->chip_id <= 0x11)
1788 stv0900_stop_all_s2_modcod(intp, demod);
1790 stv0900_activate_s2_modcod(intp, demod);
1793 stv0900_activate_s2_modcod_single(intp, demod);
1795 stv0900_set_viterbi_tracq(intp, demod);
1796 stv0900_set_viterbi_standard(intp,
1797 intp->srch_standard[demod],
1798 intp->fec[demod], demod);
1807 struct stv0900_internal *intp = state->internal;
1821 algo = intp->srch_algo[demod];
1822 stv0900_write_bits(intp, RST_HWARE, 1);
1823 stv0900_write_reg(intp, DMDISTATE, 0x5c);
1824 if (intp->chip_id >= 0x20) {
1825 if (intp->symbol_rate[demod] > 5000000)
1826 stv0900_write_reg(intp, CORRELABS, 0x9e);
1828 stv0900_write_reg(intp, CORRELABS, 0x82);
1830 stv0900_write_reg(intp, CORRELABS, 0x88);
1833 intp->symbol_rate[demod],
1834 intp->srch_algo[demod]);
1836 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
1837 intp->bw[demod] = 2 * 36000000;
1839 stv0900_write_reg(intp, TMGCFG2, 0xc0);
1840 stv0900_write_reg(intp, CORRELMANT, 0x70);
1842 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1844 stv0900_write_reg(intp, DMDT0M, 0x20);
1845 stv0900_write_reg(intp, TMGCFG, 0xd2);
1847 if (intp->symbol_rate[demod] < 2000000)
1848 stv0900_write_reg(intp, CORRELMANT, 0x63);
1850 stv0900_write_reg(intp, CORRELMANT, 0x70);
1852 stv0900_write_reg(intp, AGC2REF, 0x38);
1854 intp->bw[demod] =
1855 stv0900_carrier_width(intp->symbol_rate[demod],
1856 intp->rolloff);
1857 if (intp->chip_id >= 0x20) {
1858 stv0900_write_reg(intp, KREFTMG, 0x5a);
1860 if (intp->srch_algo[demod] == STV0900_COLD_START) {
1861 intp->bw[demod] += 10000000;
1862 intp->bw[demod] *= 15;
1863 intp->bw[demod] /= 10;
1864 } else if (intp->srch_algo[demod] == STV0900_WARM_START)
1865 intp->bw[demod] += 10000000;
1868 stv0900_write_reg(intp, KREFTMG, 0xc1);
1869 intp->bw[demod] += 10000000;
1870 intp->bw[demod] *= 15;
1871 intp->bw[demod] /= 10;
1874 stv0900_write_reg(intp, TMGCFG2, 0xc1);
1876 stv0900_set_symbol_rate(intp, intp->mclk,
1877 intp->symbol_rate[demod], demod);
1878 stv0900_set_max_symbol_rate(intp, intp->mclk,
1879 intp->symbol_rate[demod], demod);
1880 stv0900_set_min_symbol_rate(intp, intp->mclk,
1881 intp->symbol_rate[demod], demod);
1882 if (intp->symbol_rate[demod] >= 10000000)
1889 if (intp->tuner_type[demod] == 3)
1890 stv0900_set_tuner_auto(intp, intp->freq[demod],
1891 intp->bw[demod], demod);
1893 stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
1895 agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
1896 stv0900_get_bits(intp, AGCIQ_VALUE0));
1902 aq_power += (stv0900_get_bits(intp, POWER_I) +
1903 stv0900_get_bits(intp, POWER_Q)) / 2;
1909 intp->result[demod].locked = FALSE;
1913 stv0900_write_bits(intp, SPECINV_CONTROL,
1914 intp->srch_iq_inv[demod]);
1915 if (intp->chip_id <= 0x20) /*cut 2.0*/
1916 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
1918 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
1920 stv0900_set_search_standard(intp, demod);
1922 if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
1923 stv0900_start_search(intp, demod);
1929 if (intp->chip_id == 0x12) {
1930 stv0900_write_bits(intp, RST_HWARE, 0);
1932 stv0900_write_bits(intp, RST_HWARE, 1);
1933 stv0900_write_bits(intp, RST_HWARE, 0);
1941 lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
1945 if (stv0900_check_timing_lock(intp, demod) == TRUE)
1946 lock = stv0900_sw_algo(intp, demod);
1955 if (intp->chip_id <= 0x11) {
1961 stv0900_write_bits(intp, RST_HWARE, 0);
1963 stv0900_write_bits(intp, RST_HWARE, 0);
1965 stv0900_write_bits(intp, RST_HWARE, 1);
1966 stv0900_write_bits(intp, RST_HWARE, 0);
1969 } else if (intp->chip_id >= 0x20) {
1970 stv0900_write_bits(intp, RST_HWARE, 0);
1972 stv0900_write_bits(intp, RST_HWARE, 1);
1973 stv0900_write_bits(intp, RST_HWARE, 0);
1976 if (stv0900_wait_for_lock(intp, demod,
1979 intp->result[demod].locked = TRUE;
1980 if (intp->result[demod].standard ==
1982 stv0900_set_dvbs2_rolloff(intp, demod);
1983 stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
1984 stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
1985 stv0900_write_reg(intp, ERRCTRL1, 0x67);
1987 stv0900_write_reg(intp, ERRCTRL1, 0x75);
1990 stv0900_write_reg(intp, FBERCPT4, 0);
1991 stv0900_write_reg(intp, ERRCTRL2, 0xc1);
1995 no_signal = stv0900_check_signal_presence(intp, demod);
1997 intp->result[demod].locked = FALSE;
2004 if (intp->chip_id > 0x11) {
2005 intp->result[demod].locked = FALSE;
2009 if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
2010 (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))