Lines Matching defs:stv0367_writereg
122 int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
204 stv0367_writereg(state, (label >> 16) & 0xffff, reg);
251 stv0367_writereg(state, deftab[i].addr, deftab[i].value);
270 stv0367_writereg(state, R367TER_PLLMDIV, 0x1b);
271 stv0367_writereg(state, R367TER_PLLNDIV, 0xe8);
280 stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
281 stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
284 stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
285 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
290 stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
291 stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
294 stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
295 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
300 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
329 stv0367_writereg(state, R367TER_I2CRPT, tmp);
488 stv0367_writereg(state,
491 stv0367_writereg(state,
757 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
762 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
806 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
811 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
817 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
829 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
830 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
831 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
833 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
963 stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
964 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
1799 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1802 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
1803 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1804 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1805 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1806 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1807 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1808 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1809 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
1812 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1813 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
1814 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1815 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1816 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
1817 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
1818 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1819 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1822 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
1823 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1825 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1826 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1827 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
1829 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1830 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1831 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1833 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1834 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1835 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1837 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1838 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1839 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
1842 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1843 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
1844 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1845 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
1847 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1849 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1851 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
1853 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
1854 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1855 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1858 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
1859 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1860 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1862 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1864 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1866 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1868 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1869 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
1870 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1871 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1874 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1877 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1912 stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
1913 stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
1980 stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
2067 stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2068 stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2069 stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2070 stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2072 stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2299 stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2388 stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2415 stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2916 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2917 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00);
2918 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */
2919 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */
2920 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2921 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2925 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89);
2926 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
2930 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2931 stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */
2938 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2945 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2946 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01);
2947 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */
2948 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */
2949 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2950 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2954 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B);
2956 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04);
2960 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2962 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
2969 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
3160 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3169 stv0367_writereg(state, R367TER_TOPCTRL, 0x00);
3173 stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A);
3174 stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6);
3175 stv0367_writereg(state, R367TER_INC_DEROT1, 0x55);
3176 stv0367_writereg(state, R367TER_INC_DEROT2, 0x55);
3177 stv0367_writereg(state, R367TER_TRL_CTL, 0x14);
3178 stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE);
3179 stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56);
3180 stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0);
3184 stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3185 stv0367_writereg(state, R367TER_TSCFGM, 0xC0);
3186 stv0367_writereg(state, R367TER_TSCFGL, 0x20);
3187 stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */
3189 stv0367_writereg(state, R367TER_TSCFGH, 0x71);
3190 stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3192 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3195 stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */
3197 stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A);
3202 stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85);
3205 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
3212 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b);
3213 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
3216 stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23);
3218 stv0367_writereg(state, R367CAB_IQ_QAM, 0x01);
3220 stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83);
3222 stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05);
3225 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
3227 stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4)));