Lines Matching defs:state
39 static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data)
43 struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
45 ret = i2c_transfer(state->i2c, &msg, 1);
54 static int stv0297_readreg(struct stv0297_state *state, u8 reg)
59 struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1},
60 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
64 if (state->config->stop_during_read) {
65 if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
69 if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
74 if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
83 static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data)
87 val = stv0297_readreg(state, reg);
90 stv0297_writereg(state, reg, val);
95 static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len)
98 struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
100 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
104 if (state->config->stop_during_read) {
105 if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
109 if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
114 if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
123 static u32 stv0297_get_symbolrate(struct stv0297_state *state)
127 tmp = (u64)(stv0297_readreg(state, 0x55)
128 | (stv0297_readreg(state, 0x56) << 8)
129 | (stv0297_readreg(state, 0x57) << 16)
130 | (stv0297_readreg(state, 0x58) << 24));
138 static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
146 stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));
147 stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));
148 stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));
149 stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));
152 static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
168 stv0297_writereg(state, 0x60, tmp & 0xFF);
169 stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
172 static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset)
182 stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
183 stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
184 stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
185 stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
189 static long stv0297_get_carrieroffset(struct stv0297_state *state)
193 stv0297_writereg(state, 0x6B, 0x00);
195 tmp = stv0297_readreg(state, 0x66);
196 tmp |= (stv0297_readreg(state, 0x67) << 8);
197 tmp |= (stv0297_readreg(state, 0x68) << 16);
198 tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
200 tmp *= stv0297_get_symbolrate(state);
207 static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq)
219 stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
220 stv0297_writereg(state, 0x21, tmp >> 8);
221 stv0297_writereg(state, 0x20, tmp);
224 static int stv0297_set_qam(struct stv0297_state *state,
254 stv0297_writereg_mask(state, 0x00, 0x70, val << 4);
259 static int stv0297_set_inversion(struct stv0297_state *state,
277 stv0297_writereg_mask(state, 0x83, 0x08, val << 3);
284 struct stv0297_state *state = fe->demodulator_priv;
287 stv0297_writereg(state, 0x87, 0x78);
288 stv0297_writereg(state, 0x86, 0xc8);
296 struct stv0297_state *state = fe->demodulator_priv;
300 for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2)
301 stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]);
304 state->last_ber = 0;
311 struct stv0297_state *state = fe->demodulator_priv;
313 stv0297_writereg_mask(state, 0x80, 1, 1);
321 struct stv0297_state *state = fe->demodulator_priv;
323 u8 sync = stv0297_readreg(state, 0xDF);
334 struct stv0297_state *state = fe->demodulator_priv;
337 stv0297_readregs(state, 0xA0, BER, 3);
339 state->last_ber = BER[2] << 8 | BER[1];
340 stv0297_writereg_mask(state, 0xA0, 0x80, 0x80);
343 *ber = state->last_ber;
351 struct stv0297_state *state = fe->demodulator_priv;
355 stv0297_readregs(state, 0x41, STRENGTH, 3);
374 struct stv0297_state *state = fe->demodulator_priv;
377 stv0297_readregs(state, 0x07, SNR, 2);
385 struct stv0297_state *state = fe->demodulator_priv;
387 stv0297_writereg_mask(state, 0xDF, 0x03, 0x03); /* freeze the counters */
389 *ucblocks = (stv0297_readreg(state, 0xD5) << 8)
390 | stv0297_readreg(state, 0xD4);
392 stv0297_writereg_mask(state, 0xDF, 0x03, 0x02); /* clear the counters */
393 stv0297_writereg_mask(state, 0xDF, 0x03, 0x01); /* re-enable the counters */
401 struct stv0297_state *state = fe->demodulator_priv;
431 if (state->config->invert)
454 stv0297_writereg(state, 0x82, 0x0);
457 stv0297_set_initialdemodfreq(state, 7250);
460 stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
461 stv0297_writereg(state, 0x41, 0x00);
462 stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
463 stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
464 stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
465 stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
466 stv0297_writereg(state, 0x72, 0x00);
467 stv0297_writereg(state, 0x73, 0x00);
468 stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
469 stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
470 stv0297_writereg_mask(state, 0x71, 0x80, 0x00);
473 stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
474 stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
475 stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
476 stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
477 stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);
480 stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
483 stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
484 stv0297_writereg_mask(state, 0x81, 0x01, 0x00);
487 stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
488 stv0297_writereg_mask(state, 0x83, 0x20, 0x00);
491 u_threshold = stv0297_readreg(state, 0x00) & 0xf;
492 initial_u = stv0297_readreg(state, 0x01) >> 4;
493 blind_u = stv0297_readreg(state, 0x01) & 0xf;
494 stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
495 stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
496 stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
497 stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
498 stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);
501 stv0297_writereg_mask(state, 0x87, 0x80, 0x00);
504 stv0297_writereg(state, 0x63, 0x00);
505 stv0297_writereg(state, 0x64, 0x00);
506 stv0297_writereg(state, 0x65, 0x00);
507 stv0297_writereg(state, 0x66, 0x00);
508 stv0297_writereg(state, 0x67, 0x00);
509 stv0297_writereg(state, 0x68, 0x00);
510 stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
513 stv0297_set_qam(state, p->modulation);
514 stv0297_set_symbolrate(state, p->symbol_rate / 1000);
515 stv0297_set_sweeprate(state, sweeprate, p->symbol_rate / 1000);
516 stv0297_set_carrieroffset(state, carrieroffset);
517 stv0297_set_inversion(state, inversion);
523 stv0297_writereg_mask(state, 0x88, 0x08, 0x00);
525 stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
527 stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
528 stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
529 stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
530 stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
531 stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
532 stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
533 stv0297_writereg_mask(state, 0x43, 0x10, 0x10);
539 if (stv0297_readreg(state, 0x43) & 0x08)
552 if (stv0297_readreg(state, 0x82) & 0x04) {
565 if (stv0297_readreg(state, 0x82) & 0x08) {
574 stv0297_writereg_mask(state, 0x6a, 1, 0);
575 stv0297_writereg_mask(state, 0x88, 8, 0);
582 if (stv0297_readreg(state, 0xDF) & 0x80) {
592 if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
597 stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
598 state->base_freq = p->frequency;
602 stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
609 struct stv0297_state *state = fe->demodulator_priv;
612 reg_00 = stv0297_readreg(state, 0x00);
613 reg_83 = stv0297_readreg(state, 0x83);
615 p->frequency = state->base_freq;
617 if (state->config->invert)
619 p->symbol_rate = stv0297_get_symbolrate(state) * 1000;
645 struct stv0297_state *state = fe->demodulator_priv;
646 kfree(state);
654 struct stv0297_state *state = NULL;
656 /* allocate memory for the internal state */
657 state = kzalloc(sizeof(struct stv0297_state), GFP_KERNEL);
658 if (state == NULL)
661 /* setup the state */
662 state->config = config;
663 state->i2c = i2c;
664 state->last_ber = 0;
665 state->base_freq = 0;
668 if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
672 memcpy(&state->frontend.ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
673 state->frontend.demodulator_priv = state;
674 return &state->frontend;
677 kfree(state);