Lines Matching refs:state
59 static int si2165_write(struct si2165_state *state, const u16 reg,
64 dev_dbg(&state->client->dev, "i2c write: reg: 0x%04x, data: %*ph\n",
67 ret = regmap_bulk_write(state->regmap, reg, src, count);
70 dev_err(&state->client->dev, "%s: ret == %d\n", __func__, ret);
75 static int si2165_read(struct si2165_state *state,
78 int ret = regmap_bulk_read(state->regmap, reg, val, count);
81 dev_err(&state->client->dev, "%s: error (addr %02x reg %04x error (ret == %i)\n",
82 __func__, state->config.i2c_addr, reg, ret);
86 dev_dbg(&state->client->dev, "i2c read: reg: 0x%04x, data: %*ph\n",
92 static int si2165_readreg8(struct si2165_state *state,
96 int ret = regmap_read(state->regmap, reg, &val_tmp);
98 dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%02x\n", reg, *val);
102 static int si2165_readreg16(struct si2165_state *state,
107 int ret = si2165_read(state, reg, buf, 2);
109 dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%04x\n", reg, *val);
113 static int si2165_readreg24(struct si2165_state *state,
118 int ret = si2165_read(state, reg, buf, 3);
120 dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%06x\n", reg, *val);
124 static int si2165_writereg8(struct si2165_state *state, const u16 reg, u8 val)
126 return regmap_write(state->regmap, reg, val);
129 static int si2165_writereg16(struct si2165_state *state, const u16 reg, u16 val)
133 return si2165_write(state, reg, buf, 2);
136 static int si2165_writereg24(struct si2165_state *state, const u16 reg, u32 val)
140 return si2165_write(state, reg, buf, 3);
143 static int si2165_writereg32(struct si2165_state *state, const u16 reg, u32 val)
151 return si2165_write(state, reg, buf, 4);
154 static int si2165_writereg_mask8(struct si2165_state *state, const u16 reg,
159 int ret = si2165_readreg8(state, reg, &tmp);
168 return si2165_writereg8(state, reg, val);
179 static int si2165_write_reg_list(struct si2165_state *state,
187 ret = si2165_writereg8(state, regs[i].reg, regs[i].val);
201 static int si2165_init_pll(struct si2165_state *state)
203 u32 ref_freq_hz = state->config.ref_freq_hz;
242 state->fvco_hz = ref_freq_hz / divr
244 state->adc_clk = state->fvco_hz / (divm * 4u);
245 state->sys_clk = state->fvco_hz / (divl * 2u);
252 return si2165_write(state, REG_PLL_DIVL, buf, 4);
255 static int si2165_adjust_pll_divl(struct si2165_state *state, u8 divl)
257 state->sys_clk = state->fvco_hz / (divl * 2u);
258 return si2165_writereg8(state, REG_PLL_DIVL, divl);
261 static u32 si2165_get_fe_clk(struct si2165_state *state)
264 return state->adc_clk;
267 static int si2165_wait_init_done(struct si2165_state *state)
274 ret = si2165_readreg8(state, REG_INIT_DONE, &val);
281 dev_err(&state->client->dev, "init_done was not set\n");
285 static int si2165_upload_firmware_block(struct si2165_state *state,
300 dev_dbg(&state->client->dev,
304 dev_dbg(&state->client->dev,
310 dev_warn(&state->client->dev,
317 dev_warn(&state->client->dev,
325 ret = si2165_write(state, REG_DCOM_CONTROL_BYTE, buf_ctrl, 4);
328 ret = si2165_write(state, REG_DCOM_ADDR, data + offset + 4, 4);
335 ret = si2165_write(state, REG_DCOM_DATA,
345 dev_dbg(&state->client->dev,
352 dev_dbg(&state->client->dev,
361 static int si2165_upload_firmware(struct si2165_state *state)
377 switch (state->chip_revcode) {
382 dev_info(&state->client->dev, "no firmware file for revision=%d\n",
383 state->chip_revcode);
388 ret = request_firmware(&fw, fw_file, &state->client->dev);
390 dev_warn(&state->client->dev, "firmware file '%s' not found\n",
398 dev_info(&state->client->dev, "downloading firmware from file '%s' size=%d\n",
402 dev_warn(&state->client->dev, "firmware size is not multiple of 4\n");
409 dev_warn(&state->client->dev, "firmware header is missing\n");
415 dev_warn(&state->client->dev, "firmware file version is wrong\n");
426 ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);
430 ret = si2165_writereg8(state, REG_RST_ALL, 0x00);
434 ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);
439 ret = si2165_readreg8(state, REG_EN_RST_ERROR, val);
442 ret = si2165_readreg8(state, REG_EN_RST_ERROR, val);
445 ret = si2165_writereg8(state, REG_EN_RST_ERROR, 0x02);
452 dev_info(&state->client->dev, "%s: extracted patch_version=0x%02x, block_count=0x%02x, crc_expected=0x%04x\n",
455 ret = si2165_upload_firmware_block(state, data, len, &offset, 1);
459 ret = si2165_writereg8(state, REG_PATCH_VERSION, patch_version);
464 ret = si2165_writereg8(state, REG_RST_CRC, 0x01);
468 ret = si2165_upload_firmware_block(state, data, len,
471 dev_err(&state->client->dev,
477 ret = si2165_readreg16(state, REG_CRC, &val16);
482 dev_err(&state->client->dev,
489 ret = si2165_upload_firmware_block(state, data, len, &offset, 5);
494 dev_err(&state->client->dev,
502 ret = si2165_writereg_mask8(state, REG_WDOG_AND_BOOT, 0x02, 0x02);
507 ret = si2165_writereg_mask8(state, REG_EN_RST_ERROR, 0x01, 0x01);
511 dev_info(&state->client->dev, "fw load finished\n");
514 state->firmware_loaded = true;
527 struct si2165_state *state = fe->demodulator_priv;
532 dev_dbg(&state->client->dev, "%s: called\n", __func__);
535 ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);
539 ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x01);
543 ret = si2165_readreg8(state, REG_CHIP_MODE, &val);
546 if (val != state->config.chip_mode) {
547 dev_err(&state->client->dev, "could not set chip_mode\n");
552 ret = si2165_writereg8(state, REG_AGC_IF_TRI, 0x00);
555 ret = si2165_writereg8(state, REG_AGC_IF_SLR, 0x01);
558 ret = si2165_writereg8(state, REG_AGC2_OUTPUT, 0x00);
561 ret = si2165_writereg8(state, REG_AGC2_CLKDIV, 0x07);
565 ret = si2165_writereg8(state, REG_RSSI_PAD_CTRL, 0x00);
568 ret = si2165_writereg8(state, REG_RSSI_ENABLE, 0x00);
572 ret = si2165_init_pll(state);
577 ret = si2165_writereg8(state, REG_CHIP_INIT, 0x01);
581 ret = si2165_writereg8(state, REG_START_INIT, 0x01);
584 ret = si2165_wait_init_done(state);
589 ret = si2165_writereg8(state, REG_CHIP_INIT, 0x00);
594 ret = si2165_writereg16(state, REG_BER_PKT,
599 ret = si2165_readreg8(state, REG_PATCH_VERSION, &patch_version);
603 ret = si2165_writereg8(state, REG_AUTO_RESET, 0x00);
608 ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000);
612 ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, &val);
617 ret = si2165_upload_firmware(state);
623 ret = si2165_writereg8(state, REG_TS_DATA_MODE, 0x20);
626 ret = si2165_writereg16(state, REG_TS_TRI, 0x00fe);
629 ret = si2165_writereg24(state, REG_TS_SLR, 0x555555);
632 ret = si2165_writereg8(state, REG_TS_CLK_MODE, 0x01);
635 ret = si2165_writereg8(state, REG_TS_PARALLEL_MODE, 0x00);
639 c = &state->fe.dtv_property_cache;
655 struct si2165_state *state = fe->demodulator_priv;
658 ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x00);
662 ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);
673 struct si2165_state *state = fe->demodulator_priv;
682 ret = si2165_readreg8(state, REG_CHECK_SIGNAL, &u8tmp);
696 ret = si2165_readreg8(state, REG_PS_LOCK, &u8tmp);
709 ret = si2165_readreg8(state, REG_FEC_LOCK, &u8tmp);
722 ret = si2165_readreg24(state, REG_C_N, &u32tmp);
746 ret = si2165_writereg8(state, REG_BER_RST, 0x01);
760 state->ber_prev = 0;
763 ret = si2165_readreg8(state, REG_BER_AVAIL, &u8tmp);
770 ret = si2165_readreg24(state, REG_BER_BIT,
781 ret = si2165_writereg8(state,
786 dev_dbg(&state->client->dev,
812 struct si2165_state *state = fe->demodulator_priv;
820 *ber = c->post_bit_error.stat[0].uvalue - state->ber_prev;
821 state->ber_prev = c->post_bit_error.stat[0].uvalue;
826 static int si2165_set_oversamp(struct si2165_state *state, u32 dvb_rate)
834 oversamp = si2165_get_fe_clk(state);
839 dev_dbg(&state->client->dev, "Write oversamp=%#x\n", reg_value);
840 return si2165_writereg32(state, REG_OVERSAMP, reg_value);
843 static int si2165_set_if_freq_shift(struct si2165_state *state)
845 struct dvb_frontend *fe = &state->fe;
848 u32 fe_clk = si2165_get_fe_clk(state);
852 dev_err(&state->client->dev,
867 if (state->config.inversion)
873 return si2165_writereg32(state, REG_IF_FREQ_SHIFT, reg_value);
902 struct si2165_state *state = fe->demodulator_priv;
907 dev_dbg(&state->client->dev, "%s: called\n", __func__);
909 if (!state->has_dvbt)
919 ret = si2165_adjust_pll_divl(state, 12);
924 ret = si2165_writereg16(state, REG_T_BANDWIDTH, bw10k);
927 ret = si2165_set_oversamp(state, dvb_rate);
931 ret = si2165_write_reg_list(state, dvbt_regs, ARRAY_SIZE(dvbt_regs));
968 struct si2165_state *state = fe->demodulator_priv;
974 if (!state->has_dvbc)
980 ret = si2165_adjust_pll_divl(state, 14);
985 ret = si2165_set_oversamp(state, dvb_rate);
1010 ret = si2165_writereg8(state, REG_REQ_CONSTELLATION, u8tmp);
1014 ret = si2165_writereg32(state, REG_LOCK_TIMEOUT, 0x007a1200);
1018 ret = si2165_write_reg_list(state, dvbc_regs, ARRAY_SIZE(dvbc_regs));
1035 struct si2165_state *state = fe->demodulator_priv;
1042 ret = si2165_set_if_freq_shift(state);
1062 ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000);
1070 ret = si2165_set_if_freq_shift(state);
1075 ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);
1078 ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);
1083 ret = si2165_writereg8(state, REG_RST_ALL, 0x00);
1087 ret = si2165_writereg32(state, REG_GP_REG0_LSB, 0x00000000);
1092 ret = si2165_write_reg_list(state, adc_rewrite,
1098 ret = si2165_writereg8(state, REG_START_SYNCHRO, 0x01);
1102 ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);
1150 struct si2165_state *state = NULL;
1163 /* allocate memory for the internal state */
1164 state = kzalloc(sizeof(*state), GFP_KERNEL);
1165 if (!state) {
1171 state->regmap = devm_regmap_init_i2c(client, ®map_config);
1172 if (IS_ERR(state->regmap)) {
1173 ret = PTR_ERR(state->regmap);
1177 /* setup the state */
1178 state->client = client;
1179 state->config.i2c_addr = client->addr;
1180 state->config.chip_mode = pdata->chip_mode;
1181 state->config.ref_freq_hz = pdata->ref_freq_hz;
1182 state->config.inversion = pdata->inversion;
1184 if (state->config.ref_freq_hz < 4000000 ||
1185 state->config.ref_freq_hz > 27000000) {
1186 dev_err(&state->client->dev, "ref_freq of %d Hz not supported by this driver\n",
1187 state->config.ref_freq_hz);
1193 memcpy(&state->fe.ops, &si2165_ops,
1195 state->fe.ops.release = NULL;
1196 state->fe.demodulator_priv = state;
1197 i2c_set_clientdata(client, state);
1200 ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);
1204 ret = si2165_readreg8(state, REG_CHIP_MODE, &val);
1207 if (val != state->config.chip_mode)
1210 ret = si2165_readreg8(state, REG_CHIP_REVCODE, &state->chip_revcode);
1214 ret = si2165_readreg8(state, REV_CHIP_TYPE, &state->chip_type);
1219 ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);
1223 if (state->chip_revcode < 26)
1224 rev_char = 'A' + state->chip_revcode;
1228 switch (state->chip_type) {
1231 state->has_dvbt = true;
1235 state->has_dvbt = true;
1236 state->has_dvbc = true;
1239 dev_err(&state->client->dev, "Unsupported Silicon Labs chip (type %d, rev %d)\n",
1240 state->chip_type, state->chip_revcode);
1244 dev_info(&state->client->dev,
1246 chip_name, rev_char, state->chip_type,
1247 state->chip_revcode);
1249 strlcat(state->fe.ops.info.name, chip_name,
1250 sizeof(state->fe.ops.info.name));
1253 if (state->has_dvbt) {
1254 state->fe.ops.delsys[n++] = SYS_DVBT;
1255 strlcat(state->fe.ops.info.name, " DVB-T",
1256 sizeof(state->fe.ops.info.name));
1258 if (state->has_dvbc) {
1259 state->fe.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
1260 strlcat(state->fe.ops.info.name, " DVB-C",
1261 sizeof(state->fe.ops.info.name));
1265 *pdata->fe = &state->fe;
1272 kfree(state);
1279 struct si2165_state *state = i2c_get_clientdata(client);
1283 kfree(state);