Lines Matching defs:state
42 static int s5h1432_writereg(struct s5h1432_state *state,
50 ret = i2c_transfer(state->i2c, &msg, 1);
59 static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg)
70 ret = i2c_transfer(state->i2c, msg, 2);
86 struct s5h1432_state *state = fe->demodulator_priv;
91 reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);
106 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg);
112 struct s5h1432_state *state = fe->demodulator_priv;
116 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
117 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
118 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x15);
121 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
122 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
123 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x40);
126 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
127 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
128 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xe0);
131 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
132 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
133 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
136 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
137 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
138 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xED);
141 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0xAA);
142 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0xAA);
143 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEA);
153 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4,
155 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5,
157 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7,
172 struct s5h1432_state *state = fe->demodulator_priv;
174 if (p->frequency == state->current_frequency) {
176 /*state->current_frequency = p->frequency; */
200 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
202 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
224 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
226 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
230 state->current_frequency = p->frequency;
237 struct s5h1432_state *state = fe->demodulator_priv;
240 state->current_frequency = 0;
246 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);
247 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);
248 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70);
249 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80);
250 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D);
251 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30);
252 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20);
253 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B);
254 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40);
255 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84);
256 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a);
257 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3);
258 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50);
259 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c);
260 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10);
261 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);
262 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);
263 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);
264 /* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1); */
265 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);
270 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
271 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
272 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
274 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);
277 reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);
279 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);
284 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
286 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
327 struct s5h1432_state *state = fe->demodulator_priv;
328 kfree(state);
336 struct s5h1432_state *state = NULL;
339 /* allocate memory for the internal state */
340 state = kmalloc(sizeof(struct s5h1432_state), GFP_KERNEL);
341 if (!state)
344 /* setup the state */
345 state->config = config;
346 state->i2c = i2c;
347 state->current_modulation = QAM_16;
348 state->inversion = state->config->inversion;
351 memcpy(&state->frontend.ops, &s5h1432_ops,
354 state->frontend.demodulator_priv = state;
356 return &state->frontend;