Lines Matching defs:state
51 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
65 static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg)
70 { .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 },
71 { .addr = state->config->demod_address, .flags = 0, .buf = ®, .len = 1 },
72 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = 1 },
76 b[1] = state->shadow[(reg - 1) & 0xff];
78 if (state->config->repeated_start_workaround) {
79 ret = i2c_transfer(state->i2c, msg, 3);
83 ret = i2c_transfer(state->i2c, &msg[1], 1);
86 ret = i2c_transfer(state->i2c, &msg[2], 1);
91 /* dprintk("rd(%02x): %02x %02x\n", state->config->demod_address, reg, b[0]); */
96 static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
99 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
102 /* dprintk("wr(%02x): %02x %02x\n", state->config->demod_address, reg, data); */
103 err = i2c_transfer(state->i2c, &msg, 1);
108 state->shadow[reg] = data;
116 struct s5h1420_state* state = fe->demodulator_priv;
122 s5h1420_writereg(state, 0x3c,
123 (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02);
127 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03);
131 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd);
142 struct s5h1420_state* state = fe->demodulator_priv;
147 s5h1420_writereg(state, 0x3b,
148 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08);
152 s5h1420_writereg(state, 0x3b,
153 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
164 struct s5h1420_state* state = fe->demodulator_priv;
175 val = s5h1420_readreg(state, 0x3b);
176 s5h1420_writereg(state, 0x3b, 0x02);
181 s5h1420_writereg(state, 0x3d + i, cmd->msg[i]);
185 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |
191 if (!(s5h1420_readreg(state, 0x3b) & 0x08))
200 s5h1420_writereg(state, 0x3b, val);
209 struct s5h1420_state* state = fe->demodulator_priv;
217 val = s5h1420_readreg(state, 0x3b);
218 s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive mode? */
224 if (!(s5h1420_readreg(state, 0x3b) & 0x80)) /* FIXME: do we test DIS_RDY(0x08) or RCV_EN(0x80)? */
236 if (s5h1420_readreg(state, 0x49)) {
242 length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4;
251 reply->msg[i] = s5h1420_readreg(state, 0x3d + i);
256 s5h1420_writereg(state, 0x3b, val);
264 struct s5h1420_state* state = fe->demodulator_priv;
270 val = s5h1420_readreg(state, 0x3b);
271 s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01);
275 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04);
280 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);
285 if (!(s5h1420_readreg(state, 0x3b) & 0x08))
294 s5h1420_writereg(state, 0x3b, val);
299 static enum fe_status s5h1420_get_status_bits(struct s5h1420_state *state)
304 val = s5h1420_readreg(state, 0x14);
309 val = s5h1420_readreg(state, 0x36);
323 struct s5h1420_state* state = fe->demodulator_priv;
331 /* determine lock state */
332 *status = s5h1420_get_status_bits(state);
337 val = s5h1420_readreg(state, Vit10);
340 s5h1420_writereg(state, Vit09, 0x13);
342 s5h1420_writereg(state, Vit09, 0x1b);
346 *status = s5h1420_get_status_bits(state);
351 if ((*status & FE_HAS_LOCK) && !state->postlocked) {
354 u32 tmp = s5h1420_getsymbolrate(state);
355 switch (s5h1420_readreg(state, Vit10) & 0x07) {
368 tmp = state->fclk / tmp;
390 s5h1420_writereg(state, FEC01, 0x18);
391 s5h1420_writereg(state, FEC01, 0x10);
392 s5h1420_writereg(state, FEC01, val);
395 val = s5h1420_readreg(state, Mpeg02);
396 s5h1420_writereg(state, Mpeg02, val | (1 << 6));
399 val = s5h1420_readreg(state, QPSK01) & 0x7f;
400 s5h1420_writereg(state, QPSK01, val);
404 if (s5h1420_getsymbolrate(state) >= 20000000) {
405 s5h1420_writereg(state, Loop04, 0x8a);
406 s5h1420_writereg(state, Loop05, 0x6a);
408 s5h1420_writereg(state, Loop04, 0x58);
409 s5h1420_writereg(state, Loop05, 0x27);
413 state->postlocked = 1;
423 struct s5h1420_state* state = fe->demodulator_priv;
425 s5h1420_writereg(state, 0x46, 0x1d);
428 *ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
435 struct s5h1420_state* state = fe->demodulator_priv;
437 u8 val = s5h1420_readreg(state, 0x15);
446 struct s5h1420_state* state = fe->demodulator_priv;
448 s5h1420_writereg(state, 0x46, 0x1f);
451 *ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
456 static void s5h1420_reset(struct s5h1420_state* state)
459 s5h1420_writereg (state, 0x01, 0x08);
460 s5h1420_writereg (state, 0x01, 0x00);
464 static void s5h1420_setsymbolrate(struct s5h1420_state* state,
475 do_div(val, (state->fclk / 1000));
479 v = s5h1420_readreg(state, Loop01);
480 s5h1420_writereg(state, Loop01, v & 0x7f);
481 s5h1420_writereg(state, Tnco01, val >> 16);
482 s5h1420_writereg(state, Tnco02, val >> 8);
483 s5h1420_writereg(state, Tnco03, val & 0xff);
484 s5h1420_writereg(state, Loop01, v | 0x80);
488 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
490 return state->symbol_rate;
493 static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
502 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
506 v = s5h1420_readreg(state, Loop01);
507 s5h1420_writereg(state, Loop01, v & 0xbf);
508 s5h1420_writereg(state, Pnco01, val >> 16);
509 s5h1420_writereg(state, Pnco02, val >> 8);
510 s5h1420_writereg(state, Pnco03, val & 0xff);
511 s5h1420_writereg(state, Loop01, v | 0x40);
515 static int s5h1420_getfreqoffset(struct s5h1420_state* state)
519 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
520 val = s5h1420_readreg(state, 0x0e) << 16;
521 val |= s5h1420_readreg(state, 0x0f) << 8;
522 val |= s5h1420_readreg(state, 0x10);
523 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
530 val = (((-val) * (state->fclk/1000000)) / (1<<24));
535 static void s5h1420_setfec_inversion(struct s5h1420_state* state,
544 inversion = state->config->invert ? 0x08 : 0;
546 inversion = state->config->invert ? 0 : 0x08;
589 s5h1420_writereg(state, Vit08, vit08);
590 s5h1420_writereg(state, Vit09, vit09);
594 static enum fe_code_rate s5h1420_getfec(struct s5h1420_state *state)
596 switch(s5h1420_readreg(state, 0x32) & 0x07) {
620 s5h1420_getinversion(struct s5h1420_state *state)
622 if (s5h1420_readreg(state, 0x32) & 0x08)
631 struct s5h1420_state* state = fe->demodulator_priv;
639 frequency_delta = p->frequency - state->tunedfreq;
643 (state->fec_inner == p->fec_inner) &&
644 (state->symbol_rate == p->symbol_rate)) {
654 s5h1420_setfreqoffset(state, p->frequency - tmp);
656 s5h1420_setfreqoffset(state, 0);
664 s5h1420_reset(state);
668 state->fclk = 80000000;
670 state->fclk = 59000000;
672 state->fclk = 86000000;
674 state->fclk = 88000000;
676 state->fclk = 44000000;
678 dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
679 s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8);
680 s5h1420_writereg(state, PLL02, 0x40);
681 s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
685 s5h1420_writereg(state, QPSK01, 0xae | 0x10);
687 s5h1420_writereg(state, QPSK01, 0xac | 0x10);
690 s5h1420_writereg(state, CON_1, 0x00);
691 s5h1420_writereg(state, QPSK02, 0x00);
692 s5h1420_writereg(state, Pre01, 0xb0);
694 s5h1420_writereg(state, Loop01, 0xF0);
695 s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
696 s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
698 s5h1420_writereg(state, Loop04, 0x79);
700 s5h1420_writereg(state, Loop04, 0x58);
701 s5h1420_writereg(state, Loop05, 0x6b);
704 s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
706 s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
708 s5h1420_writereg(state, Post01, (3 << 6) | 0x10);
710 s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */
712 s5h1420_writereg(state, Sync01, 0x33);
713 s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity);
714 s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */
715 s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */
717 s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */
718 s5h1420_writereg(state, DiS03, 0x00);
719 s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */
726 s5h1420_setfreqoffset(state, 0);
730 s5h1420_setsymbolrate(state, p);
731 s5h1420_setfec_inversion(state, p);
734 s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);
736 state->fec_inner = p->fec_inner;
737 state->symbol_rate = p->symbol_rate;
738 state->postlocked = 0;
739 state->tunedfreq = p->frequency;
748 struct s5h1420_state* state = fe->demodulator_priv;
750 p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state);
751 p->inversion = s5h1420_getinversion(state);
752 p->symbol_rate = s5h1420_getsymbolrate(state);
753 p->fec_inner = s5h1420_getfec(state);
793 struct s5h1420_state* state = fe->demodulator_priv;
796 return s5h1420_writereg(state, 0x02, state->CON_1_val | 1);
798 return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe);
803 struct s5h1420_state* state = fe->demodulator_priv;
806 state->CON_1_val = state->config->serial_mpeg << 4;
807 s5h1420_writereg(state, 0x02, state->CON_1_val);
809 s5h1420_reset(state);
816 struct s5h1420_state* state = fe->demodulator_priv;
817 state->CON_1_val = 0x12;
818 return s5h1420_writereg(state, 0x02, state->CON_1_val);
823 struct s5h1420_state* state = fe->demodulator_priv;
824 i2c_del_adapter(&state->tuner_i2c_adapter);
825 kfree(state);
835 struct s5h1420_state *state = i2c_get_adapdata(i2c_adap);
837 u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition */
848 m[0].addr = state->config->demod_address;
854 return i2c_transfer(state->i2c, m, 1 + num) == 1 + num ? num : -EIO;
864 struct s5h1420_state *state = fe->demodulator_priv;
865 return &state->tuner_i2c_adapter;
874 /* allocate memory for the internal state */
875 struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
878 if (state == NULL)
881 /* setup the state */
882 state->config = config;
883 state->i2c = i2c;
884 state->postlocked = 0;
885 state->fclk = 88000000;
886 state->tunedfreq = 0;
887 state->fec_inner = FEC_NONE;
888 state->symbol_rate = 0;
891 i = s5h1420_readreg(state, ID01);
895 memset(state->shadow, 0xff, sizeof(state->shadow));
898 state->shadow[i] = s5h1420_readreg(state, i);
901 memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
902 state->frontend.demodulator_priv = state;
905 strscpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus",
906 sizeof(state->tuner_i2c_adapter.name));
907 state->tuner_i2c_adapter.algo = &s5h1420_tuner_i2c_algo;
908 state->tuner_i2c_adapter.algo_data = NULL;
909 i2c_set_adapdata(&state->tuner_i2c_adapter, state);
910 if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
915 return &state->frontend;
918 kfree(state);