Lines Matching defs:s5h1420_writereg
96 static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
122 s5h1420_writereg(state, 0x3c,
127 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03);
131 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd);
147 s5h1420_writereg(state, 0x3b,
152 s5h1420_writereg(state, 0x3b,
176 s5h1420_writereg(state, 0x3b, 0x02);
181 s5h1420_writereg(state, 0x3d + i, cmd->msg[i]);
185 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |
200 s5h1420_writereg(state, 0x3b, val);
218 s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive mode? */
256 s5h1420_writereg(state, 0x3b, val);
271 s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01);
275 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04);
280 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);
294 s5h1420_writereg(state, 0x3b, val);
340 s5h1420_writereg(state, Vit09, 0x13);
342 s5h1420_writereg(state, Vit09, 0x1b);
390 s5h1420_writereg(state, FEC01, 0x18);
391 s5h1420_writereg(state, FEC01, 0x10);
392 s5h1420_writereg(state, FEC01, val);
396 s5h1420_writereg(state, Mpeg02, val | (1 << 6));
400 s5h1420_writereg(state, QPSK01, val);
405 s5h1420_writereg(state, Loop04, 0x8a);
406 s5h1420_writereg(state, Loop05, 0x6a);
408 s5h1420_writereg(state, Loop04, 0x58);
409 s5h1420_writereg(state, Loop05, 0x27);
425 s5h1420_writereg(state, 0x46, 0x1d);
448 s5h1420_writereg(state, 0x46, 0x1f);
459 s5h1420_writereg (state, 0x01, 0x08);
460 s5h1420_writereg (state, 0x01, 0x00);
480 s5h1420_writereg(state, Loop01, v & 0x7f);
481 s5h1420_writereg(state, Tnco01, val >> 16);
482 s5h1420_writereg(state, Tnco02, val >> 8);
483 s5h1420_writereg(state, Tnco03, val & 0xff);
484 s5h1420_writereg(state, Loop01, v | 0x80);
507 s5h1420_writereg(state, Loop01, v & 0xbf);
508 s5h1420_writereg(state, Pnco01, val >> 16);
509 s5h1420_writereg(state, Pnco02, val >> 8);
510 s5h1420_writereg(state, Pnco03, val & 0xff);
511 s5h1420_writereg(state, Loop01, v | 0x40);
519 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
523 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
589 s5h1420_writereg(state, Vit08, vit08);
590 s5h1420_writereg(state, Vit09, vit09);
679 s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8);
680 s5h1420_writereg(state, PLL02, 0x40);
681 s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
685 s5h1420_writereg(state, QPSK01, 0xae | 0x10);
687 s5h1420_writereg(state, QPSK01, 0xac | 0x10);
690 s5h1420_writereg(state, CON_1, 0x00);
691 s5h1420_writereg(state, QPSK02, 0x00);
692 s5h1420_writereg(state, Pre01, 0xb0);
694 s5h1420_writereg(state, Loop01, 0xF0);
695 s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
696 s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
698 s5h1420_writereg(state, Loop04, 0x79);
700 s5h1420_writereg(state, Loop04, 0x58);
701 s5h1420_writereg(state, Loop05, 0x6b);
704 s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
706 s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
708 s5h1420_writereg(state, Post01, (3 << 6) | 0x10);
710 s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */
712 s5h1420_writereg(state, Sync01, 0x33);
713 s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity);
714 s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */
715 s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */
717 s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */
718 s5h1420_writereg(state, DiS03, 0x00);
719 s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */
734 s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);
796 return s5h1420_writereg(state, 0x02, state->CON_1_val | 1);
798 return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe);
807 s5h1420_writereg(state, 0x02, state->CON_1_val);
818 return s5h1420_writereg(state, 0x02, state->CON_1_val);