Lines Matching defs:state
330 static int s5h1411_writereg(struct s5h1411_state *state,
338 ret = i2c_transfer(state->i2c, &msg, 1);
347 static u16 s5h1411_readreg(struct s5h1411_state *state, u8 addr, u8 reg)
357 ret = i2c_transfer(state->i2c, msg, 2);
367 struct s5h1411_state *state = fe->demodulator_priv;
371 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 0);
372 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 1);
378 struct s5h1411_state *state = fe->demodulator_priv;
384 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x10d5);
385 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x5342);
386 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x10d9);
389 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1225);
390 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x1e96);
391 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1225);
394 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x14bc);
395 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0xb53e);
396 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x14bd);
404 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1be4);
405 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x3655);
406 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1be4);
410 state->if_freq = KHz;
417 struct s5h1411_state *state = fe->demodulator_priv;
422 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbe) & 0xcfff;
442 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbe, val);
447 struct s5h1411_state *state = fe->demodulator_priv;
451 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x24) & ~0x1000;
456 state->inversion = inversion;
457 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x24, val);
462 struct s5h1411_state *state = fe->demodulator_priv;
466 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbd) & ~0x100;
471 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbd, val);
477 struct s5h1411_state *state = fe->demodulator_priv;
481 if ((state->first_tune == 0) && (m == state->current_modulation)) {
490 s5h1411_set_if_freq(fe, state->config->vsb_if);
491 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x71);
492 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x00);
493 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0xf1);
499 s5h1411_set_if_freq(fe, state->config->qam_if);
500 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x0171);
501 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x0001);
502 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x16, 0x1101);
503 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0x00f0);
510 state->current_modulation = m;
511 state->first_tune = 0;
519 struct s5h1411_state *state = fe->demodulator_priv;
524 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
526 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 0);
531 struct s5h1411_state *state = fe->demodulator_priv;
536 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xe0) & ~0x02;
539 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0,
542 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, val);
547 struct s5h1411_state *state = fe->demodulator_priv;
552 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 1);
554 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 0);
568 struct s5h1411_state *state = fe->demodulator_priv;
572 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf3, 0);
579 struct s5h1411_state *state = fe->demodulator_priv;
585 state->current_frequency = p->frequency;
607 to a default state. */
610 struct s5h1411_state *state = fe->demodulator_priv;
619 s5h1411_writereg(state, init_tab[i].addr,
624 state->current_modulation = VSB_8;
629 state->first_tune = 1;
631 if (state->config->output_mode == S5H1411_SERIAL_OUTPUT)
638 s5h1411_set_spectralinversion(fe, state->config->inversion);
639 s5h1411_set_if_freq(fe, state->config->vsb_if);
640 s5h1411_set_gpio(fe, state->config->gpio);
641 s5h1411_set_mpeg_timing(fe, state->config->mpeg_timing);
652 struct s5h1411_state *state = fe->demodulator_priv;
660 switch (state->current_modulation) {
663 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf0);
671 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf2);
677 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x53);
686 switch (state->config->status_mode) {
760 struct s5h1411_state *state = fe->demodulator_priv;
764 switch (state->current_modulation) {
766 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1);
769 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1);
772 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR,
819 struct s5h1411_state *state = fe->demodulator_priv;
821 *ucblocks = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xc9);
834 struct s5h1411_state *state = fe->demodulator_priv;
836 p->frequency = state->current_frequency;
837 p->modulation = state->current_modulation;
851 struct s5h1411_state *state = fe->demodulator_priv;
852 kfree(state);
860 struct s5h1411_state *state = NULL;
863 /* allocate memory for the internal state */
864 state = kzalloc(sizeof(struct s5h1411_state), GFP_KERNEL);
865 if (state == NULL)
868 /* setup the state */
869 state->config = config;
870 state->i2c = i2c;
871 state->current_modulation = VSB_8;
872 state->inversion = state->config->inversion;
875 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x05);
880 memcpy(&state->frontend.ops, &s5h1411_ops,
883 state->frontend.demodulator_priv = state;
885 if (s5h1411_init(&state->frontend) != 0) {
892 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
895 s5h1411_set_powerstate(&state->frontend, 1);
897 return &state->frontend;
900 kfree(state);