Lines Matching defs:state
36 /* QAM tuning state goes through the following state transitions */
301 static int s5h1409_writereg(struct s5h1409_state *state, u8 reg, u16 data)
306 struct i2c_msg msg = { .addr = state->config->demod_address,
309 ret = i2c_transfer(state->i2c, &msg, 1);
318 static u16 s5h1409_readreg(struct s5h1409_state *state, u8 reg)
325 { .addr = state->config->demod_address, .flags = 0,
327 { .addr = state->config->demod_address, .flags = I2C_M_RD,
330 ret = i2c_transfer(state->i2c, msg, 2);
339 struct s5h1409_state *state = fe->demodulator_priv;
343 s5h1409_writereg(state, 0xf5, 0);
344 s5h1409_writereg(state, 0xf5, 1);
345 state->is_qam_locked = 0;
346 state->qam_state = QAM_STATE_UNTUNED;
351 #define S5H1409_QAM_IF_FREQ (state->config->qam_if)
355 struct s5h1409_state *state = fe->demodulator_priv;
361 s5h1409_writereg(state, 0x87, 0x014b);
362 s5h1409_writereg(state, 0x88, 0x0cb5);
363 s5h1409_writereg(state, 0x89, 0x03e2);
368 s5h1409_writereg(state, 0x87, 0x01be);
369 s5h1409_writereg(state, 0x88, 0x0436);
370 s5h1409_writereg(state, 0x89, 0x054d);
373 state->if_freq = KHz;
380 struct s5h1409_state *state = fe->demodulator_priv;
385 return s5h1409_writereg(state, 0x1b, 0x1101); /* Inverted */
387 return s5h1409_writereg(state, 0x1b, 0x0110); /* Normal */
393 struct s5h1409_state *state = fe->demodulator_priv;
400 if (state->if_freq != S5H1409_VSB_IF_FREQ)
402 s5h1409_writereg(state, 0xf4, 0);
408 if (state->if_freq != S5H1409_QAM_IF_FREQ)
410 s5h1409_writereg(state, 0xf4, 1);
411 s5h1409_writereg(state, 0x85, 0x110);
418 state->current_modulation = m;
426 struct s5h1409_state *state = fe->demodulator_priv;
431 return s5h1409_writereg(state, 0xf3, 1);
433 return s5h1409_writereg(state, 0xf3, 0);
438 struct s5h1409_state *state = fe->demodulator_priv;
443 return s5h1409_writereg(state, 0xe3,
444 s5h1409_readreg(state, 0xe3) | 0x1100);
446 return s5h1409_writereg(state, 0xe3,
447 s5h1409_readreg(state, 0xe3) & 0xfeff);
452 struct s5h1409_state *state = fe->demodulator_priv;
456 return s5h1409_writereg(state, 0xf2, enable);
461 struct s5h1409_state *state = fe->demodulator_priv;
465 return s5h1409_writereg(state, 0xfa, 0);
470 struct s5h1409_state *state = fe->demodulator_priv;
473 if (state->qam_state < QAM_STATE_INTERLEAVE_SET) {
479 if (state->qam_state == QAM_STATE_QAM_OPTIMIZED_L3) {
486 reg = s5h1409_readreg(state, 0xf0);
491 s5h1409_writereg(state, 0x96, 0x000c);
493 if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L3) {
494 dprintk("%s() setting QAM state to OPT_L3\n",
496 s5h1409_writereg(state, 0x93, 0x3130);
497 s5h1409_writereg(state, 0x9e, 0x2836);
498 state->qam_state = QAM_STATE_QAM_OPTIMIZED_L3;
501 if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L2) {
502 dprintk("%s() setting QAM state to OPT_L2\n",
504 s5h1409_writereg(state, 0x93, 0x3332);
505 s5h1409_writereg(state, 0x9e, 0x2c37);
506 state->qam_state = QAM_STATE_QAM_OPTIMIZED_L2;
511 if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L1) {
512 dprintk("%s() setting QAM state to OPT_L1\n", __func__);
513 s5h1409_writereg(state, 0x96, 0x0008);
514 s5h1409_writereg(state, 0x93, 0x3332);
515 s5h1409_writereg(state, 0x9e, 0x2c37);
516 state->qam_state = QAM_STATE_QAM_OPTIMIZED_L1;
523 struct s5h1409_state *state = fe->demodulator_priv;
526 if (state->is_qam_locked)
530 reg = s5h1409_readreg(state, 0xf0);
534 state->is_qam_locked = 1;
537 s5h1409_writereg(state, 0x96, 0x00c);
539 s5h1409_writereg(state, 0x93, 0x3332);
540 s5h1409_writereg(state, 0x9e, 0x2c37);
542 s5h1409_writereg(state, 0x93, 0x3130);
543 s5h1409_writereg(state, 0x9e, 0x2836);
547 s5h1409_writereg(state, 0x96, 0x0008);
548 s5h1409_writereg(state, 0x93, 0x3332);
549 s5h1409_writereg(state, 0x9e, 0x2c37);
555 struct s5h1409_state *state = fe->demodulator_priv;
558 if (state->qam_state >= QAM_STATE_INTERLEAVE_SET) {
563 reg = s5h1409_readreg(state, 0xf1);
567 if (state->qam_state == QAM_STATE_UNTUNED ||
568 state->qam_state == QAM_STATE_TUNING_STARTED) {
569 dprintk("%s() setting QAM state to INTERLEAVE_SET\n",
571 reg1 = s5h1409_readreg(state, 0xb2);
572 reg2 = s5h1409_readreg(state, 0xad);
574 s5h1409_writereg(state, 0x96, 0x0020);
575 s5h1409_writereg(state, 0xad,
577 state->qam_state = QAM_STATE_INTERLEAVE_SET;
580 if (state->qam_state == QAM_STATE_UNTUNED) {
581 dprintk("%s() setting QAM state to TUNING_STARTED\n",
583 s5h1409_writereg(state, 0x96, 0x08);
584 s5h1409_writereg(state, 0xab,
585 s5h1409_readreg(state, 0xab) | 0x1001);
586 state->qam_state = QAM_STATE_TUNING_STARTED;
593 struct s5h1409_state *state = fe->demodulator_priv;
596 reg = s5h1409_readreg(state, 0xf1);
600 if (state->qam_state != 2) {
601 state->qam_state = 2;
602 reg1 = s5h1409_readreg(state, 0xb2);
603 reg2 = s5h1409_readreg(state, 0xad);
605 s5h1409_writereg(state, 0x96, 0x20);
606 s5h1409_writereg(state, 0xad,
608 s5h1409_writereg(state, 0xab,
609 s5h1409_readreg(state, 0xab) & 0xeffe);
612 if (state->qam_state != 1) {
613 state->qam_state = 1;
614 s5h1409_writereg(state, 0x96, 0x08);
615 s5h1409_writereg(state, 0xab,
616 s5h1409_readreg(state, 0xab) | 0x1001);
625 struct s5h1409_state *state = fe->demodulator_priv;
631 state->current_frequency = p->frequency;
648 if (state->current_modulation != VSB_8) {
652 if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
666 struct s5h1409_state *state = fe->demodulator_priv;
671 val = s5h1409_readreg(state, 0xac) & 0xcfff;
691 return s5h1409_writereg(state, 0xac, val);
695 to a default state. */
700 struct s5h1409_state *state = fe->demodulator_priv;
707 s5h1409_writereg(state, init_tab[i].reg, init_tab[i].data);
710 state->current_modulation = VSB_8;
715 if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
717 s5h1409_writereg(state, 0x09, 0x0050);
720 s5h1409_writereg(state, 0x21, 0x0001);
721 s5h1409_writereg(state, 0x50, 0x030e);
724 s5h1409_writereg(state, 0x82, 0x0800);
727 if (state->config->output_mode == S5H1409_SERIAL_OUTPUT)
728 s5h1409_writereg(state, 0xab,
729 s5h1409_readreg(state, 0xab) | 0x100); /* Serial */
731 s5h1409_writereg(state, 0xab,
732 s5h1409_readreg(state, 0xab) & 0xfeff); /* Parallel */
734 s5h1409_set_spectralinversion(fe, state->config->inversion);
735 s5h1409_set_if_freq(fe, state->if_freq);
736 s5h1409_set_gpio(fe, state->config->gpio);
737 s5h1409_set_mpeg_timing(fe, state->config->mpeg_timing);
748 struct s5h1409_state *state = fe->demodulator_priv;
755 if (state->current_modulation != VSB_8) {
759 if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
766 reg = s5h1409_readreg(state, 0xf1);
772 switch (state->config->status_mode) {
846 struct s5h1409_state *state = fe->demodulator_priv;
850 switch (state->current_modulation) {
852 reg = s5h1409_readreg(state, 0xf0) & 0xff;
855 reg = s5h1409_readreg(state, 0xf0) & 0xff;
858 reg = s5h1409_readreg(state, 0xf1) & 0x3ff;
904 struct s5h1409_state *state = fe->demodulator_priv;
906 *ucblocks = s5h1409_readreg(state, 0xb5);
919 struct s5h1409_state *state = fe->demodulator_priv;
921 p->frequency = state->current_frequency;
922 p->modulation = state->current_modulation;
936 struct s5h1409_state *state = fe->demodulator_priv;
937 kfree(state);
945 struct s5h1409_state *state = NULL;
948 /* allocate memory for the internal state */
949 state = kzalloc(sizeof(struct s5h1409_state), GFP_KERNEL);
950 if (state == NULL)
953 /* setup the state */
954 state->config = config;
955 state->i2c = i2c;
956 state->current_modulation = 0;
957 state->if_freq = S5H1409_VSB_IF_FREQ;
960 reg = s5h1409_readreg(state, 0x04);
965 memcpy(&state->frontend.ops, &s5h1409_ops,
967 state->frontend.demodulator_priv = state;
969 if (s5h1409_init(&state->frontend) != 0) {
976 s5h1409_i2c_gate_ctrl(&state->frontend, 1);
978 return &state->frontend;
981 kfree(state);