Lines Matching refs:state
147 static int i2cread(struct mxl *state, u8 *data, int len)
149 return i2c_read(state->base->i2c, state->base->adr, data, len);
152 static int i2cwrite(struct mxl *state, u8 *data, int len)
154 return i2c_write(state->base->i2c, state->base->adr, data, len);
157 static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val)
166 stat = i2cwrite(state, data,
169 dev_err(state->i2cdev, "i2c read error 1\n");
171 stat = i2cread(state, (u8 *) val,
175 dev_err(state->i2cdev, "i2c read error 2\n");
182 static int send_command(struct mxl *state, u32 size, u8 *buf)
187 mutex_lock(&state->base->i2c_lock);
188 if (state->base->fwversion > 0x02010109) {
189 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val);
191 dev_info(state->i2cdev, "%s busy\n", __func__);
193 mutex_unlock(&state->base->i2c_lock);
195 mutex_lock(&state->base->i2c_lock);
196 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR,
200 dev_info(state->i2cdev, "%s busy\n", __func__);
201 mutex_unlock(&state->base->i2c_lock);
205 stat = i2cwrite(state, buf, size);
206 mutex_unlock(&state->base->i2c_lock);
210 static int write_register(struct mxl *state, u32 reg, u32 val)
218 mutex_lock(&state->base->i2c_lock);
219 stat = i2cwrite(state, data, sizeof(data));
220 mutex_unlock(&state->base->i2c_lock);
222 dev_err(state->i2cdev, "i2c write error\n");
226 static int write_firmware_block(struct mxl *state,
230 u8 *buf = state->base->buf;
232 mutex_lock(&state->base->i2c_lock);
240 stat = i2cwrite(state, buf,
243 mutex_unlock(&state->base->i2c_lock);
245 dev_err(state->i2cdev, "fw block write failed\n");
249 static int read_register(struct mxl *state, u32 reg, u32 *val)
258 mutex_lock(&state->base->i2c_lock);
259 stat = i2cwrite(state, data,
262 dev_err(state->i2cdev, "i2c read error 1\n");
264 stat = i2cread(state, (u8 *) val,
266 mutex_unlock(&state->base->i2c_lock);
269 dev_err(state->i2cdev, "i2c read error 2\n");
273 static int read_register_block(struct mxl *state, u32 reg, u32 size, u8 *data)
276 u8 *buf = state->base->buf;
278 mutex_lock(&state->base->i2c_lock);
286 stat = i2cwrite(state, buf,
289 stat = i2cread(state, data, size);
292 mutex_unlock(&state->base->i2c_lock);
296 static int read_by_mnemonic(struct mxl *state,
302 stat = read_register(state, reg, &data);
313 static int update_by_mnemonic(struct mxl *state,
319 stat = read_register(state, reg, &data);
324 stat = write_register(state, reg, data);
328 static int firmware_is_alive(struct mxl *state)
332 if (read_register(state, HYDRA_HEAR_BEAT, &hb0))
335 if (read_register(state, HYDRA_HEAR_BEAT, &hb1))
365 struct mxl *state = fe->demodulator_priv;
367 list_del(&state->mxl);
369 state->base->count--;
370 if (state->base->count == 0) {
371 list_del(&state->base->mxllist);
372 kfree(state->base);
374 kfree(state);
393 static int cfg_scrambler(struct mxl *state, u32 gold)
399 state->demod, 0, 0, 0,
411 return send_command(state, sizeof(buf), buf);
414 static int cfg_demod_abort_tune(struct mxl *state)
420 abort_tune_cmd.demod_id = state->demod;
423 return send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
430 /*struct mxl *state = fe->demodulator_priv;*/
432 return 0; /*CfgDemodAbortTune(state);*/
437 struct mxl *state = fe->demodulator_priv;
450 /* CfgDemodAbortTune(state); */
471 cfg_scrambler(state, p->scrambling_sequence_index);
476 demod_chan_cfg.tuner_index = state->tuner;
477 demod_chan_cfg.demod_index = state->demod;
484 mutex_lock(&state->base->tune_lock);
486 state->base->next_tune))
487 while (time_before(jiffies, state->base->next_tune))
489 state->base->next_tune = jiffies + msecs_to_jiffies(100);
490 state->tuner_in_use = state->tuner;
493 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
495 mutex_unlock(&state->base->tune_lock);
499 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable);
503 struct mxl *state = fe->demodulator_priv;
506 cfg_demod_abort_tune(state);
507 if (state->tuner_in_use != 0xffffffff) {
508 mutex_lock(&state->base->tune_lock);
509 state->tuner_in_use = 0xffffffff;
510 list_for_each_entry(p, &state->base->mxls, mxl) {
511 if (p->tuner_in_use == state->tuner)
514 if (&p->mxl == &state->base->mxls)
515 enable_tuner(state, state->tuner, 0);
516 mutex_unlock(&state->base->tune_lock);
523 struct mxl *state = fe->demodulator_priv;
528 mutex_lock(&state->base->status_lock);
529 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
530 stat = read_register(state, (HYDRA_DMD_SNR_ADDR_OFFSET +
531 HYDRA_DMD_STATUS_OFFSET(state->demod)),
533 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
534 mutex_unlock(&state->base->status_lock);
544 struct mxl *state = fe->demodulator_priv;
548 mutex_lock(&state->base->status_lock);
549 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
550 read_register_block(state,
552 HYDRA_DMD_STATUS_OFFSET(state->demod)),
555 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
569 read_register_block(state,
571 HYDRA_DMD_STATUS_OFFSET(state->demod)),
593 mutex_unlock(&state->base->status_lock);
600 struct mxl *state = fe->demodulator_priv;
605 mutex_lock(&state->base->status_lock);
606 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
607 stat = read_register(state, (HYDRA_DMD_STATUS_INPUT_POWER_ADDR +
608 HYDRA_DMD_STATUS_OFFSET(state->demod)),
610 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
611 mutex_unlock(&state->base->status_lock);
621 struct mxl *state = fe->demodulator_priv;
625 mutex_lock(&state->base->status_lock);
626 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
627 read_register(state, (HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET +
628 HYDRA_DMD_STATUS_OFFSET(state->demod)),
630 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
631 mutex_unlock(&state->base->status_lock);
661 struct mxl *state = fe->demodulator_priv;
669 state->tune_time = jiffies;
691 struct mxl *state = fe->demodulator_priv;
695 mutex_lock(&state->base->status_lock);
696 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
697 read_register_block(state,
699 HYDRA_DMD_STATUS_OFFSET(state->demod)),
703 read_register_block(state,
705 HYDRA_DMD_STATUS_OFFSET(state->demod)),
708 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
709 mutex_unlock(&state->base->status_lock);
711 dev_dbg(state->i2cdev, "freq=%u delsys=%u srate=%u\n",
777 struct mxl *state = fe->demodulator_priv;
779 state->tuner = input;
816 static void cfg_dev_xtal(struct mxl *state, u32 freq, u32 cap, u32 enable)
818 if (state->base->can_clkout || !enable)
819 update_by_mnemonic(state, 0x90200054, 23, 1, enable);
822 write_register(state, HYDRA_CRYSTAL_SETTING, 0);
824 write_register(state, HYDRA_CRYSTAL_SETTING, 1);
826 write_register(state, HYDRA_CRYSTAL_CAP, cap);
850 static int write_fw_segment(struct mxl *state,
874 status = write_firmware_block(state, mem_addr, size, w_buf_ptr);
885 static int do_firmware_download(struct mxl *state, u8 *mbin_buffer_ptr,
898 dev_err(state->i2cdev, "%s: Invalid file header ID (%c)\n",
902 status = write_register(state, FW_DL_SIGN_ADDR, 0);
908 dev_err(state->i2cdev, "%s: Invalid segment header ID (%c)\n",
917 if (state->base->type == MXL_HYDRA_DEVICE_568) {
921 update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
923 write_register(state, 0x90720000, 0);
927 status = write_fw_segment(state, seg_address,
933 status = write_fw_segment(state, seg_address,
944 static int check_fw(struct mxl *state, u8 *mbin, u32 mbin_len)
953 dev_info(state->i2cdev, "Invalid FW Header\n");
960 dev_info(state->i2cdev, "Invalid FW Checksum\n");
966 static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len)
974 if (check_fw(state, mbin, mbin_len))
978 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 0);
984 status = write_register(state, HYDRA_RESET_TRANSPORT_FIFO_REG,
988 status = write_register(state, HYDRA_RESET_BBAND_REG,
992 status = write_register(state, HYDRA_RESET_XBAR_REG,
1000 status = write_register(state, HYDRA_MODULES_CLK_2_REG,
1005 status = read_register(state, HYDRA_PRCM_ROOT_CLK_REG, ®_data);
1008 status = do_firmware_download(state, mbin, mbin_len);
1012 if (state->base->type == MXL_HYDRA_DEVICE_568) {
1016 status = write_register(state, 0x90720000, 1);
1022 status = write_register(state, 0x9076B510, 1);
1027 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
1035 status = write_register(state, XPT_DMD0_BASEADDR, 0x76543210);
1039 if (!firmware_is_alive(state))
1042 dev_info(state->i2cdev, "Hydra FW alive. Hail!\n");
1049 dev_sku_cfg.sku_type = state->base->sku_type;
1052 status = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
1058 static int cfg_ts_pad_mux(struct mxl *state, enum MXL_BOOL_E enable_serial_ts)
1065 if ((state->base->type == MXL_HYDRA_DEVICE_541) ||
1066 (state->base->type == MXL_HYDRA_DEVICE_541S))
1069 if ((state->base->type == MXL_HYDRA_DEVICE_581) ||
1070 (state->base->type == MXL_HYDRA_DEVICE_581S))
1076 switch (state->base->type) {
1083 status |= update_by_mnemonic(state, 0x90000170, 24, 3,
1085 status |= update_by_mnemonic(state, 0x90000170, 28, 3,
1087 status |= update_by_mnemonic(state, 0x90000174, 0, 3,
1089 status |= update_by_mnemonic(state, 0x90000174, 4, 3,
1091 status |= update_by_mnemonic(state, 0x90000174, 8, 3,
1093 status |= update_by_mnemonic(state, 0x90000174, 12, 3,
1095 status |= update_by_mnemonic(state, 0x90000174, 16, 3,
1097 status |= update_by_mnemonic(state, 0x90000174, 20, 3,
1099 status |= update_by_mnemonic(state, 0x90000174, 24, 3,
1101 status |= update_by_mnemonic(state, 0x90000174, 28, 3,
1103 status |= update_by_mnemonic(state, 0x90000178, 0, 3,
1105 status |= update_by_mnemonic(state, 0x90000178, 4, 3,
1107 status |= update_by_mnemonic(state, 0x90000178, 8, 3,
1113 status |= update_by_mnemonic(state, 0x9000016C, 4, 3, 1);
1114 status |= update_by_mnemonic(state, 0x9000016C, 8, 3, 0);
1115 status |= update_by_mnemonic(state, 0x9000016C, 12, 3, 0);
1116 status |= update_by_mnemonic(state, 0x9000016C, 16, 3, 0);
1117 status |= update_by_mnemonic(state, 0x90000170, 0, 3, 0);
1118 status |= update_by_mnemonic(state, 0x90000178, 12, 3, 1);
1119 status |= update_by_mnemonic(state, 0x90000178, 16, 3, 1);
1120 status |= update_by_mnemonic(state, 0x90000178, 20, 3, 1);
1121 status |= update_by_mnemonic(state, 0x90000178, 24, 3, 1);
1122 status |= update_by_mnemonic(state, 0x9000017C, 0, 3, 1);
1123 status |= update_by_mnemonic(state, 0x9000017C, 4, 3, 1);
1125 status |= update_by_mnemonic(state,
1127 status |= update_by_mnemonic(state,
1129 status |= update_by_mnemonic(state,
1131 status |= update_by_mnemonic(state,
1133 status |= update_by_mnemonic(state,
1135 status |= update_by_mnemonic(state,
1137 status |= update_by_mnemonic(state,
1139 status |= update_by_mnemonic(state,
1141 status |= update_by_mnemonic(state,
1143 status |= update_by_mnemonic(state,
1145 status |= update_by_mnemonic(state,
1147 status |= update_by_mnemonic(state,
1149 status |= update_by_mnemonic(state,
1151 status |= update_by_mnemonic(state,
1153 status |= update_by_mnemonic(state,
1155 status |= update_by_mnemonic(state,
1157 status |= update_by_mnemonic(state,
1159 status |= update_by_mnemonic(state,
1162 status |= update_by_mnemonic(state,
1164 status |= update_by_mnemonic(state,
1166 status |= update_by_mnemonic(state,
1168 status |= update_by_mnemonic(state,
1170 status |= update_by_mnemonic(state,
1172 status |= update_by_mnemonic(state,
1174 status |= update_by_mnemonic(state,
1176 status |= update_by_mnemonic(state,
1178 status |= update_by_mnemonic(state,
1180 status |= update_by_mnemonic(state,
1182 status |= update_by_mnemonic(state,
1184 status |= update_by_mnemonic(state,
1186 status |= update_by_mnemonic(state,
1188 status |= update_by_mnemonic(state,
1190 status |= update_by_mnemonic(state,
1192 status |= update_by_mnemonic(state,
1194 status |= update_by_mnemonic(state,
1196 status |= update_by_mnemonic(state,
1203 status |= update_by_mnemonic(state,
1205 status |= update_by_mnemonic(state,
1207 status |= update_by_mnemonic(state,
1209 status |= update_by_mnemonic(state,
1211 status |= update_by_mnemonic(state,
1213 status |= update_by_mnemonic(state,
1215 status |= update_by_mnemonic(state,
1217 status |= update_by_mnemonic(state,
1219 status |= update_by_mnemonic(state,
1221 status |= update_by_mnemonic(state,
1223 status |= update_by_mnemonic(state,
1225 status |= update_by_mnemonic(state,
1228 status |= update_by_mnemonic(state,
1230 status |= update_by_mnemonic(state,
1232 status |= update_by_mnemonic(state,
1234 status |= update_by_mnemonic(state,
1236 status |= update_by_mnemonic(state,
1238 status |= update_by_mnemonic(state,
1240 status |= update_by_mnemonic(state,
1242 status |= update_by_mnemonic(state,
1244 status |= update_by_mnemonic(state,
1246 status |= update_by_mnemonic(state,
1248 status |= update_by_mnemonic(state,
1251 status |= update_by_mnemonic(state,
1253 status |= update_by_mnemonic(state,
1255 status |= update_by_mnemonic(state,
1257 status |= update_by_mnemonic(state,
1259 status |= update_by_mnemonic(state,
1261 status |= update_by_mnemonic(state,
1263 status |= update_by_mnemonic(state,
1265 status |= update_by_mnemonic(state,
1268 status |= update_by_mnemonic(state,
1270 status |= update_by_mnemonic(state,
1272 status |= update_by_mnemonic(state,
1274 status |= update_by_mnemonic(state,
1276 status |= update_by_mnemonic(state,
1278 status |= update_by_mnemonic(state,
1280 status |= update_by_mnemonic(state,
1282 status |= update_by_mnemonic(state,
1284 status |= update_by_mnemonic(state,
1286 status |= update_by_mnemonic(state,
1288 status |= update_by_mnemonic(state,
1296 status |= update_by_mnemonic(state,
1298 status |= update_by_mnemonic(state,
1300 status |= update_by_mnemonic(state,
1302 status |= update_by_mnemonic(state,
1304 status |= update_by_mnemonic(state,
1306 status |= update_by_mnemonic(state,
1308 status |= update_by_mnemonic(state,
1310 status |= update_by_mnemonic(state,
1312 status |= update_by_mnemonic(state,
1314 status |= update_by_mnemonic(state,
1316 status |= update_by_mnemonic(state,
1323 static int set_drive_strength(struct mxl *state,
1329 read_register(state, 0x90000194, &val);
1330 dev_info(state->i2cdev, "DIGIO = %08x\n", val);
1331 dev_info(state->i2cdev, "set drive_strength = %u\n", ts_drive_strength);
1334 stat |= update_by_mnemonic(state, 0x90000194, 0, 3, ts_drive_strength);
1335 stat |= update_by_mnemonic(state, 0x90000194, 20, 3, ts_drive_strength);
1336 stat |= update_by_mnemonic(state, 0x90000194, 24, 3, ts_drive_strength);
1337 stat |= update_by_mnemonic(state, 0x90000198, 12, 3, ts_drive_strength);
1338 stat |= update_by_mnemonic(state, 0x90000198, 16, 3, ts_drive_strength);
1339 stat |= update_by_mnemonic(state, 0x90000198, 20, 3, ts_drive_strength);
1340 stat |= update_by_mnemonic(state, 0x90000198, 24, 3, ts_drive_strength);
1341 stat |= update_by_mnemonic(state, 0x9000019C, 0, 3, ts_drive_strength);
1342 stat |= update_by_mnemonic(state, 0x9000019C, 4, 3, ts_drive_strength);
1343 stat |= update_by_mnemonic(state, 0x9000019C, 8, 3, ts_drive_strength);
1344 stat |= update_by_mnemonic(state, 0x9000019C, 24, 3, ts_drive_strength);
1345 stat |= update_by_mnemonic(state, 0x9000019C, 28, 3, ts_drive_strength);
1346 stat |= update_by_mnemonic(state, 0x900001A0, 0, 3, ts_drive_strength);
1347 stat |= update_by_mnemonic(state, 0x900001A0, 4, 3, ts_drive_strength);
1348 stat |= update_by_mnemonic(state, 0x900001A0, 20, 3, ts_drive_strength);
1349 stat |= update_by_mnemonic(state, 0x900001A0, 24, 3, ts_drive_strength);
1350 stat |= update_by_mnemonic(state, 0x900001A0, 28, 3, ts_drive_strength);
1355 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable)
1367 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
1371 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1374 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1378 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1379 dev_dbg(state->i2cdev, "tuner %u ready = %u\n",
1386 static int config_ts(struct mxl *state, enum MXL_HYDRA_DEMOD_ID_E demod_id,
1449 demod_id = state->base->ts_map[demod_id];
1455 cfg_ts_pad_mux(state, MXL_TRUE);
1456 update_by_mnemonic(state,
1464 if (state->base->chipversion >= 2) {
1465 status |= update_by_mnemonic(state,
1471 update_by_mnemonic(state, 0x90700044, 16, 8, nco_count_min);
1477 status |= update_by_mnemonic(state,
1483 update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type);
1485 status |= update_by_mnemonic(state,
1491 status |= update_by_mnemonic(state,
1497 status |= update_by_mnemonic(state,
1503 status |= update_by_mnemonic(state,
1509 status |= update_by_mnemonic(state,
1515 status |= update_by_mnemonic(state,
1523 status |= update_by_mnemonic(state,
1528 status |= update_by_mnemonic(state,
1536 status |= update_by_mnemonic(state,
1542 status |= update_by_mnemonic(state,
1551 status |= update_by_mnemonic(state,
1557 status |= update_by_mnemonic(state,
1568 status |= update_by_mnemonic(state,
1577 static int config_mux(struct mxl *state)
1579 update_by_mnemonic(state, 0x9070000C, 0, 1, 0);
1580 update_by_mnemonic(state, 0x9070000C, 1, 1, 0);
1581 update_by_mnemonic(state, 0x9070000C, 2, 1, 0);
1582 update_by_mnemonic(state, 0x9070000C, 3, 1, 0);
1583 update_by_mnemonic(state, 0x9070000C, 4, 1, 0);
1584 update_by_mnemonic(state, 0x9070000C, 5, 1, 0);
1585 update_by_mnemonic(state, 0x9070000C, 6, 1, 0);
1586 update_by_mnemonic(state, 0x9070000C, 7, 1, 0);
1587 update_by_mnemonic(state, 0x90700008, 0, 2, 1);
1588 update_by_mnemonic(state, 0x90700008, 2, 2, 1);
1592 static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg)
1598 return firmware_download(state, cfg->fw, cfg->fw_len);
1608 stat = firmware_download(state, buf, 0x40000);
1614 static int validate_sku(struct mxl *state)
1618 u32 type = state->base->type;
1620 status = read_by_mnemonic(state, 0x90000190, 0, 3, &pad_mux_bond);
1621 status |= read_by_mnemonic(state, 0x80030000, 0, 12, &prcm_chip_id);
1622 status |= read_by_mnemonic(state, 0x80030004, 24, 8, &prcm_so_cid);
1626 dev_info(state->i2cdev, "padMuxBond=%08x, prcmChipId=%08x, prcmSoCId=%08x\n",
1635 state->base->type = MXL_HYDRA_DEVICE_581;
1662 static int get_fwinfo(struct mxl *state)
1667 status = read_by_mnemonic(state, 0x90000190, 0, 3, &val);
1670 dev_info(state->i2cdev, "chipID=%08x\n", val);
1672 status = read_by_mnemonic(state, 0x80030004, 8, 8, &val);
1675 dev_info(state->i2cdev, "chipVer=%08x\n", val);
1677 status = read_register(state, HYDRA_FIRMWARE_VERSION, &val);
1680 dev_info(state->i2cdev, "FWVer=%08x\n", val);
1682 state->base->fwversion = val;
1709 static int probe(struct mxl *state, struct mxl5xx_cfg *cfg)
1715 state->base->ts_map = ts_map1_to_1;
1717 switch (state->base->type) {
1720 state->base->can_clkout = 1;
1721 state->base->demod_num = 8;
1722 state->base->tuner_num = 1;
1723 state->base->sku_type = MXL_HYDRA_SKU_TYPE_581;
1726 state->base->can_clkout = 1;
1727 state->base->demod_num = 8;
1728 state->base->tuner_num = 3;
1729 state->base->sku_type = MXL_HYDRA_SKU_TYPE_582;
1732 state->base->can_clkout = 0;
1733 state->base->demod_num = 8;
1734 state->base->tuner_num = 4;
1735 state->base->sku_type = MXL_HYDRA_SKU_TYPE_585;
1738 state->base->can_clkout = 0;
1739 state->base->demod_num = 4;
1740 state->base->tuner_num = 4;
1741 state->base->sku_type = MXL_HYDRA_SKU_TYPE_544;
1742 state->base->ts_map = ts_map54x;
1746 state->base->can_clkout = 0;
1747 state->base->demod_num = 4;
1748 state->base->tuner_num = 1;
1749 state->base->sku_type = MXL_HYDRA_SKU_TYPE_541;
1750 state->base->ts_map = ts_map54x;
1754 state->base->can_clkout = 0;
1755 state->base->demod_num = 6;
1756 state->base->tuner_num = 1;
1757 state->base->sku_type = MXL_HYDRA_SKU_TYPE_561;
1760 state->base->can_clkout = 0;
1761 state->base->demod_num = 8;
1762 state->base->tuner_num = 1;
1763 state->base->chan_bond = 1;
1764 state->base->sku_type = MXL_HYDRA_SKU_TYPE_568;
1767 state->base->can_clkout = 1;
1768 state->base->demod_num = 4;
1769 state->base->tuner_num = 3;
1770 state->base->sku_type = MXL_HYDRA_SKU_TYPE_542;
1771 state->base->ts_map = ts_map54x;
1776 state->base->can_clkout = 0;
1777 state->base->demod_num = 8;
1778 state->base->tuner_num = 4;
1779 state->base->sku_type = MXL_HYDRA_SKU_TYPE_584;
1783 status = validate_sku(state);
1787 update_by_mnemonic(state, 0x80030014, 9, 1, 1);
1788 update_by_mnemonic(state, 0x8003003C, 12, 1, 1);
1789 status = read_by_mnemonic(state, 0x80030000, 12, 4, &chipver);
1791 state->base->chipversion = 0;
1793 state->base->chipversion = (chipver == 2) ? 2 : 1;
1794 dev_info(state->i2cdev, "Hydra chip version %u\n",
1795 state->base->chipversion);
1797 cfg_dev_xtal(state, cfg->clk, cfg->cap, 0);
1799 fw = firmware_is_alive(state);
1801 status = load_fw(state, cfg);
1805 get_fwinfo(state);
1807 config_mux(state);
1826 for (j = 0; j < state->base->demod_num; j++) {
1827 status = config_ts(state, (enum MXL_HYDRA_DEMOD_ID_E) j,
1832 set_drive_strength(state, 1);
1840 struct mxl *state;
1843 state = kzalloc(sizeof(struct mxl), GFP_KERNEL);
1844 if (!state)
1847 state->demod = demod;
1848 state->tuner = tuner;
1849 state->tuner_in_use = 0xffffffff;
1850 state->i2cdev = &i2c->dev;
1857 state->base = base;
1871 state->base = base;
1872 if (probe(state, cfg) < 0) {
1878 state->fe.ops = mxl_ops;
1879 state->xbar[0] = 4;
1880 state->xbar[1] = demod;
1881 state->xbar[2] = 8;
1882 state->fe.demodulator_priv = state;
1885 list_add(&state->mxl, &base->mxls);
1886 return &state->fe;
1889 kfree(state);