Lines Matching defs:state
50 static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
57 msg[0].addr = state->config->demod_address;
61 msg[1].addr = state->config->demod_address;
66 ret = i2c_transfer(state->i2c, msg, 2);
84 static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg,
108 msg.addr = state->config->demod_address;
113 ret = i2c_transfer(state->i2c, &msg, 1);
123 static inline int mt312_readreg(struct mt312_state *state,
126 return mt312_read(state, reg, val, 1);
129 static inline int mt312_writereg(struct mt312_state *state,
135 return mt312_write(state, reg, &tmp, 1);
138 static int mt312_reset(struct mt312_state *state, const u8 full)
140 return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
143 static int mt312_get_inversion(struct mt312_state *state,
149 ret = mt312_readreg(state, VIT_MODE, &vit_mode);
159 static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr)
168 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
174 ret = mt312_writereg(state, MON_CTRL, 0x03);
178 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
187 ret = mt312_writereg(state, MON_CTRL, 0x05);
191 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
197 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
206 (((state->xtal * 8192) / (sym_rat_op + 8192)) *
213 static int mt312_get_code_rate(struct mt312_state *state, enum fe_code_rate *cr)
222 ret = mt312_readreg(state, FEC_STATUS, &fec_status);
233 struct mt312_state *state = fe->demodulator_priv;
238 ret = mt312_writereg(state, CONFIG,
239 (state->freq_mult == 6 ? 0x88 : 0x8c));
247 ret = mt312_reset(state, 1);
257 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
262 switch (state->id) {
265 ret = mt312_writereg(state, GPP_CTRL, 0x80);
272 ret = mt312_write(state, HW_CTRL, buf, 2);
277 ret = mt312_writereg(state, HW_CTRL, 0x00);
281 ret = mt312_writereg(state, MPEG_CTRL, 0x00);
289 buf[0] = DIV_ROUND_CLOSEST(state->xtal * state->freq_mult * 2, 1000000);
292 buf[1] = DIV_ROUND_CLOSEST(state->xtal, 22000 * 4);
294 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
298 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
303 switch (state->id) {
312 ret = mt312_writereg(state, OP_CTRL, buf[0]);
320 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
324 ret = mt312_writereg(state, CS_SW_LIM, 0x69);
334 struct mt312_state *state = fe->demodulator_priv;
341 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
345 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
349 ret = mt312_writereg(state, DISEQC_MODE,
360 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
371 struct mt312_state *state = fe->demodulator_priv;
380 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
384 ret = mt312_writereg(state, DISEQC_MODE,
395 struct mt312_state *state = fe->demodulator_priv;
404 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
408 ret = mt312_writereg(state, DISEQC_MODE,
419 struct mt312_state *state = fe->demodulator_priv;
427 if (state->config->voltage_inverted)
430 return mt312_writereg(state, DISEQC_MODE, val);
435 struct mt312_state *state = fe->demodulator_priv;
441 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
464 struct mt312_state *state = fe->demodulator_priv;
468 ret = mt312_read(state, RS_BERCNT_H, buf, 3);
480 struct mt312_state *state = fe->demodulator_priv;
486 ret = mt312_read(state, AGC_H, buf, sizeof(buf));
502 struct mt312_state *state = fe->demodulator_priv;
506 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf));
517 struct mt312_state *state = fe->demodulator_priv;
521 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf));
533 struct mt312_state *state = fe->demodulator_priv;
564 switch (state->id) {
570 ret = mt312_readreg(state, CONFIG, &config_val);
575 if (state->freq_mult == 6) {
577 state->freq_mult = 9;
583 if (state->freq_mult == 9) {
585 state->freq_mult = 6;
626 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
630 ret = mt312_reset(state, 0);
640 struct mt312_state *state = fe->demodulator_priv;
643 ret = mt312_get_inversion(state, &p->inversion);
647 ret = mt312_get_symbol_rate(state, &p->symbol_rate);
651 ret = mt312_get_code_rate(state, &p->fec_inner);
660 struct mt312_state *state = fe->demodulator_priv;
665 switch (state->id) {
667 ret = mt312_readreg(state, GPP_CTRL, &val);
681 ret = mt312_writereg(state, GPP_CTRL, val);
689 struct mt312_state *state = fe->demodulator_priv;
694 ret = mt312_reset(state, 1);
698 if (state->id == ID_ZL10313) {
700 ret = mt312_writereg(state, GPP_CTRL, 0x00);
705 ret = mt312_writereg(state, HW_CTRL, 0x0d);
710 ret = mt312_readreg(state, CONFIG, &config);
715 ret = mt312_writereg(state, CONFIG, config & 0x7f);
733 struct mt312_state *state = fe->demodulator_priv;
734 kfree(state);
780 struct mt312_state *state = NULL;
782 /* allocate memory for the internal state */
783 state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL);
784 if (state == NULL)
787 /* setup the state */
788 state->config = config;
789 state->i2c = i2c;
792 if (mt312_readreg(state, ID, &state->id) < 0)
796 memcpy(&state->frontend.ops, &mt312_ops,
798 state->frontend.demodulator_priv = state;
800 switch (state->id) {
802 strscpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S",
803 sizeof(state->frontend.ops.info.name));
804 state->xtal = MT312_PLL_CLK;
805 state->freq_mult = 9;
808 strscpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S",
809 sizeof(state->frontend.ops.info.name));
810 state->xtal = MT312_PLL_CLK;
811 state->freq_mult = 6;
814 strscpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S",
815 sizeof(state->frontend.ops.info.name));
816 state->xtal = MT312_PLL_CLK_10_111;
817 state->freq_mult = 9;
824 return &state->frontend;
827 kfree(state);