Lines Matching refs:target_mclk
632 u32 tuner_frequency_khz, target_mclk, u32tmp;
702 target_mclk = 96000000;
704 target_mclk = 144000000;
708 m88ds3103b_set_mclk(dev, target_mclk / 1000);
723 target_mclk = dev->cfg->ts_clk;
728 target_mclk = 96000000;
731 target_mclk = 96000000;
733 target_mclk = 144000000;
735 target_mclk = 192000000;
744 switch (target_mclk) {
911 u16tmp = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk);
916 dev_dbg(&client->dev, "target_mclk=%u ts_clk=%u ts_clk_divide_ratio=%u\n",
917 target_mclk, dev->cfg->ts_clk, u16tmp);
938 m88ds3103b_set_mclk(dev, target_mclk / 1000);