Lines Matching refs:ret
54 #define lg_chkerr(ret) \
57 __ret = (ret < 0); \
59 pr_err("error %d on line %d\n", ret, __LINE__); \
125 int ret;
134 ret = i2c_transfer(state->i2c_adap, &msg, 1);
136 if (ret != 1) {
138 msg.buf[0], msg.buf[1], msg.buf[2], ret);
139 if (ret < 0)
140 return ret;
149 int ret;
158 ret = i2c_transfer(state->i2c_adap, msg, 2);
160 if (ret != 2) {
161 pr_err("error (addr %02x reg %04x error (ret == %i)\n",
162 state->cfg->i2c_addr, reg, ret);
163 if (ret < 0)
164 return ret;
176 int ret = lgdt3306a_read_reg(state, reg, &__val); \
177 if (lg_chkerr(ret)) \
186 int ret;
190 ret = lgdt3306a_read_reg(state, reg, &val);
191 if (lg_chkerr(ret))
197 ret = lgdt3306a_write_reg(state, reg, val);
198 lg_chkerr(ret);
200 return ret;
207 int ret;
211 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
212 if (lg_chkerr(ret))
216 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
217 lg_chkerr(ret);
220 return ret;
227 int ret;
231 ret = lgdt3306a_set_reg_bit(state, 0x0071, 7,
233 if (lg_chkerr(ret))
240 ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0);
241 if (lg_chkerr(ret))
244 ret = lgdt3306a_read_reg(state, 0x0070, &val);
245 if (lg_chkerr(ret))
253 ret = lgdt3306a_write_reg(state, 0x0070, val);
254 lg_chkerr(ret);
257 return ret;
265 int ret;
269 ret = lgdt3306a_read_reg(state, 0x0070, &val);
270 if (lg_chkerr(ret))
280 ret = lgdt3306a_write_reg(state, 0x0070, val);
281 lg_chkerr(ret);
284 return ret;
291 int ret;
296 ret = lgdt3306a_read_reg(state, 0x0070, &val);
297 if (lg_chkerr(ret))
304 ret = lgdt3306a_write_reg(state, 0x0070, val);
305 if (lg_chkerr(ret))
309 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1);
310 if (lg_chkerr(ret))
315 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0);
316 if (lg_chkerr(ret))
319 ret = lgdt3306a_read_reg(state, 0x0070, &val);
320 if (lg_chkerr(ret))
324 ret = lgdt3306a_write_reg(state, 0x0070, val);
325 if (lg_chkerr(ret))
330 return ret;
346 int ret;
352 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
353 if (lg_chkerr(ret))
357 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0);
358 if (lg_chkerr(ret))
363 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
364 if (lg_chkerr(ret))
368 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1);
369 if (lg_chkerr(ret))
377 return ret;
384 int ret;
389 ret = lgdt3306a_read_reg(state, 0x0002, &val);
392 ret = lgdt3306a_write_reg(state, 0x0002, val);
393 if (lg_chkerr(ret))
397 ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
398 if (lg_chkerr(ret))
402 ret = lgdt3306a_read_reg(state, 0x0009, &val);
405 ret = lgdt3306a_write_reg(state, 0x0009, val);
406 if (lg_chkerr(ret))
410 ret = lgdt3306a_read_reg(state, 0x0009, &val);
412 ret = lgdt3306a_write_reg(state, 0x0009, val);
413 if (lg_chkerr(ret))
417 ret = lgdt3306a_read_reg(state, 0x000d, &val);
419 ret = lgdt3306a_write_reg(state, 0x000d, val);
420 if (lg_chkerr(ret))
426 ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
427 if (lg_chkerr(ret))
431 ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
432 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
433 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
436 ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
437 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
438 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
441 ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
442 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
443 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
446 ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
447 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
448 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
454 ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
455 if (lg_chkerr(ret))
459 ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
460 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
461 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
464 ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
465 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
466 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
469 ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
470 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
471 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
474 ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
475 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
476 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
479 ret = lgdt3306a_read_reg(state, 0x001e, &val);
482 ret = lgdt3306a_write_reg(state, 0x001e, val);
484 ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
486 ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
488 ret = lgdt3306a_read_reg(state, 0x211f, &val);
490 ret = lgdt3306a_write_reg(state, 0x211f, val);
492 ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
494 ret = lgdt3306a_read_reg(state, 0x1061, &val);
497 ret = lgdt3306a_write_reg(state, 0x1061, val);
499 ret = lgdt3306a_read_reg(state, 0x103d, &val);
501 ret = lgdt3306a_write_reg(state, 0x103d, val);
503 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
505 ret = lgdt3306a_read_reg(state, 0x2141, &val);
507 ret = lgdt3306a_write_reg(state, 0x2141, val);
509 ret = lgdt3306a_read_reg(state, 0x2135, &val);
512 ret = lgdt3306a_write_reg(state, 0x2135, val);
514 ret = lgdt3306a_read_reg(state, 0x0003, &val);
516 ret = lgdt3306a_write_reg(state, 0x0003, val);
518 ret = lgdt3306a_read_reg(state, 0x001c, &val);
520 ret = lgdt3306a_write_reg(state, 0x001c, val);
523 ret = lgdt3306a_read_reg(state, 0x2179, &val);
525 ret = lgdt3306a_write_reg(state, 0x2179, val);
527 ret = lgdt3306a_read_reg(state, 0x217a, &val);
529 ret = lgdt3306a_write_reg(state, 0x217a, val);
532 ret = lgdt3306a_soft_reset(state);
533 if (lg_chkerr(ret))
538 return ret;
544 int ret;
549 ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
550 if (lg_chkerr(ret))
554 ret = lgdt3306a_read_reg(state, 0x0002, &val);
557 ret = lgdt3306a_write_reg(state, 0x0002, val);
558 if (lg_chkerr(ret))
562 ret = lgdt3306a_read_reg(state, 0x0009, &val);
564 ret = lgdt3306a_write_reg(state, 0x0009, val);
565 if (lg_chkerr(ret))
569 ret = lgdt3306a_read_reg(state, 0x0009, &val);
577 ret = lgdt3306a_write_reg(state, 0x0009, val);
578 if (lg_chkerr(ret))
582 ret = lgdt3306a_read_reg(state, 0x101a, &val);
589 ret = lgdt3306a_write_reg(state, 0x101a, val);
590 if (lg_chkerr(ret))
594 ret = lgdt3306a_read_reg(state, 0x000d, &val);
597 ret = lgdt3306a_write_reg(state, 0x000d, val);
598 if (lg_chkerr(ret))
602 ret = lgdt3306a_read_reg(state, 0x0024, &val);
604 ret = lgdt3306a_write_reg(state, 0x0024, val);
605 if (lg_chkerr(ret))
609 ret = lgdt3306a_read_reg(state, 0x000a, &val);
612 ret = lgdt3306a_write_reg(state, 0x000a, val);
613 if (lg_chkerr(ret))
617 ret = lgdt3306a_read_reg(state, 0x2849, &val);
619 ret = lgdt3306a_write_reg(state, 0x2849, val);
620 if (lg_chkerr(ret))
624 ret = lgdt3306a_read_reg(state, 0x302b, &val);
626 ret = lgdt3306a_write_reg(state, 0x302b, val);
627 if (lg_chkerr(ret))
631 ret = lgdt3306a_soft_reset(state);
632 if (lg_chkerr(ret))
637 return ret;
643 int ret;
649 ret = lgdt3306a_set_vsb(state);
654 ret = lgdt3306a_set_qam(state, p->modulation);
659 if (lg_chkerr(ret))
665 return ret;
694 int ret;
698 ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
699 return ret;
705 int ret;
710 ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);
711 return ret;
718 int ret = 0;
727 ret = lgdt3306a_set_inversion(state, inversion);
732 ret = lgdt3306a_set_inversion_auto(state, 0);
738 ret = lgdt3306a_set_inversion_auto(state, 1);
741 ret = -EINVAL;
744 return ret;
750 int ret;
793 ret = lgdt3306a_write_reg(state, 0x0010, nco1);
794 if (ret)
795 return ret;
796 ret = lgdt3306a_write_reg(state, 0x0011, nco2);
797 if (ret)
798 return ret;
823 int ret;
828 ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
829 if (lg_chkerr(ret))
832 ret = lgdt3306a_power(state, 0); /* power down */
833 lg_chkerr(ret);
851 int ret;
856 ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
857 if (lg_chkerr(ret))
861 ret = lgdt3306a_set_inversion_auto(state, 0);
862 if (lg_chkerr(ret))
866 ret = lgdt3306a_set_inversion(state, 1);
867 if (lg_chkerr(ret))
873 ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1);
874 if (lg_chkerr(ret))
880 ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0);
881 if (lg_chkerr(ret))
887 ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0);
888 if (lg_chkerr(ret))
894 ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0);
895 if (lg_chkerr(ret))
900 ret = lgdt3306a_read_reg(state, 0x0005, &val);
901 if (lg_chkerr(ret))
905 ret = lgdt3306a_write_reg(state, 0x0005, val);
906 if (lg_chkerr(ret))
908 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
909 if (lg_chkerr(ret))
913 ret = lgdt3306a_read_reg(state, 0x000d, &val);
914 if (lg_chkerr(ret))
918 ret = lgdt3306a_write_reg(state, 0x000d, val);
919 if (lg_chkerr(ret))
924 ret = lgdt3306a_read_reg(state, 0x0005, &val);
925 if (lg_chkerr(ret))
929 ret = lgdt3306a_write_reg(state, 0x0005, val);
930 if (lg_chkerr(ret))
932 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
933 if (lg_chkerr(ret))
937 ret = lgdt3306a_read_reg(state, 0x000d, &val);
938 if (lg_chkerr(ret))
942 ret = lgdt3306a_write_reg(state, 0x000d, val);
943 if (lg_chkerr(ret))
949 ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
950 ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
954 ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
955 ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
958 ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
961 ret = lgdt3306a_read_reg(state, 0x103c, &val);
964 ret = lgdt3306a_write_reg(state, 0x103c, val);
967 ret = lgdt3306a_read_reg(state, 0x103d, &val);
970 ret = lgdt3306a_write_reg(state, 0x103d, val);
973 ret = lgdt3306a_read_reg(state, 0x1036, &val);
976 ret = lgdt3306a_write_reg(state, 0x1036, val);
979 ret = lgdt3306a_read_reg(state, 0x211f, &val);
981 ret = lgdt3306a_write_reg(state, 0x211f, val);
984 ret = lgdt3306a_read_reg(state, 0x2849, &val);
986 ret = lgdt3306a_write_reg(state, 0x2849, val);
989 ret = lgdt3306a_set_vsb(state);
992 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
995 ret = lgdt3306a_mpeg_tristate(state, 1);
998 ret = lgdt3306a_sleep(state);
999 lg_chkerr(ret);
1005 return ret;
1012 int ret;
1024 ret = lgdt3306a_power(state, 1); /* power up */
1025 if (lg_chkerr(ret))
1029 ret = fe->ops.tuner_ops.set_params(fe);
1033 if (lg_chkerr(ret))
1039 ret = lgdt3306a_set_modulation(state, p);
1040 if (lg_chkerr(ret))
1043 ret = lgdt3306a_agc_setup(state, p);
1044 if (lg_chkerr(ret))
1047 ret = lgdt3306a_set_if(state, p);
1048 if (lg_chkerr(ret))
1051 ret = lgdt3306a_spectral_inversion(state, p,
1053 if (lg_chkerr(ret))
1056 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
1057 if (lg_chkerr(ret))
1060 ret = lgdt3306a_mpeg_mode_polarity(state,
1063 if (lg_chkerr(ret))
1066 ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
1067 if (lg_chkerr(ret))
1070 ret = lgdt3306a_soft_reset(state);
1071 if (lg_chkerr(ret))
1079 return ret;
1108 int ret;
1112 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1113 if (ret)
1114 return ret;
1117 ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
1118 if (ret)
1119 return ret;
1121 ret = lgdt3306a_read_reg(state, 0x2191, &val);
1122 if (ret)
1123 return ret;
1126 ret = lgdt3306a_read_reg(state, 0x2180, &val);
1127 if (ret)
1128 return ret;
1131 ret = lgdt3306a_read_reg(state, 0x2181, &val);
1132 if (ret)
1133 return ret;
1140 ret = lgdt3306a_read_reg(state, 0x1061, &val);
1141 if (ret)
1142 return ret;
1152 ret = lgdt3306a_write_reg(state, 0x1061, val);
1153 if (ret)
1154 return ret;
1157 ret = lgdt3306a_read_reg(state, 0x0024, &val);
1158 if (ret)
1159 return ret;
1164 ret = lgdt3306a_write_reg(state, 0x0024, val);
1165 if (ret)
1166 return ret;
1169 ret = lgdt3306a_read_reg(state, 0x103d, &val);
1170 if (ret)
1171 return ret;
1174 ret = lgdt3306a_write_reg(state, 0x103d, val);
1176 return ret;
1183 int ret;
1185 ret = lgdt3306a_read_reg(state, 0x0081, &val);
1186 if (ret)
1194 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1195 if (ret)
1215 int ret;
1224 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1225 if (ret)
1226 return ret;
1238 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1239 if (ret)
1240 return ret;
1254 ret = lgdt3306a_read_reg(state, 0x1094, &val);
1255 if (ret)
1256 return ret;
1272 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1273 if (ret)
1274 return ret;
1300 int ret;
1303 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1304 if (ret)
1305 return ret;
1316 int ret;
1320 ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
1321 if (ret)
1322 return ret;
1325 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1326 if (ret)
1327 return ret;
1331 ret = lgdt3306a_read_reg(state, 0x2199, &val);
1332 if (ret)
1333 return ret;
1336 ret = lgdt3306a_read_reg(state, 0x0090, &val);
1337 if (ret)
1338 return ret;
1349 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1350 if (ret)
1351 return ret;
1354 ret = lgdt3306a_write_reg(state, 0x2135, val);
1355 if (ret)
1356 return ret;
1358 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1359 if (ret)
1360 return ret;
1363 ret = lgdt3306a_write_reg(state, 0x2141, val);
1364 if (ret)
1365 return ret;
1367 ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
1368 if (ret)
1369 return ret;
1371 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1372 if (ret)
1373 return ret;
1376 ret = lgdt3306a_write_reg(state, 0x2135, val);
1377 if (ret)
1378 return ret;
1380 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1381 if (ret)
1382 return ret;
1385 ret = lgdt3306a_write_reg(state, 0x2141, val);
1386 if (ret)
1387 return ret;
1389 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
1390 if (ret)
1391 return ret;
1461 int ret;
1463 ret = lgdt3306a_read_reg(state, 0x00fa, &val);
1464 if (ret)
1465 return ret;
1545 int ret;
1557 ret = lgdt3306a_pre_monitoring(state);
1558 if (ret)
1606 int ret = 0;
1609 ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
1610 if (ret == 0)
1639 ret = lgdt3306a_monitor_vsb(state);
1643 ret = -EINVAL;
1655 return ret;
1679 int ret;
1693 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1694 if (lg_chkerr(ret))
1706 ret = fe->ops.read_snr(fe, &snr);
1707 if (lg_chkerr(ret))
1726 return ret;
1769 int ret = 0;
1776 ret = lgdt3306a_set_parameters(fe);
1777 if (ret != 0)
1778 return ret;
1781 ret = lgdt3306a_read_status(fe, status);
1783 return ret;
1798 int ret;
1801 ret = lgdt3306a_set_parameters(fe);
1802 if (ret)
1805 ret = lgdt3306a_read_status(fe, &status);
1806 if (ret)
1816 dbg_info("failed (%d)\n", ret);
1834 int ret;
1855 ret = lgdt3306a_read_reg(state, 0x0000, &val);
1856 if (lg_chkerr(ret))
1865 ret = lgdt3306a_read_reg(state, 0x0001, &val);
1866 if (lg_chkerr(ret))
1875 ret = lgdt3306a_read_reg(state, 0x0002, &val);
1876 if (lg_chkerr(ret))
2214 int ret;
2219 ret = -ENOMEM;
2226 ret = -ENODEV;
2239 ret = -ENOMEM;
2243 ret = i2c_mux_add_adapter(state->muxc, 0, 0, 0);
2244 if (ret)
2261 dev_warn(&client->dev, "probe failed = %d\n", ret);
2262 return ret;