Lines Matching refs:state
101 static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val)
106 .addr = state->cfg->i2c_addr, .flags = 0,
112 ret = i2c_transfer(state->i2c_adap, &msg, 1);
125 static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val)
130 { .addr = state->cfg->i2c_addr,
132 { .addr = state->cfg->i2c_addr,
138 ret = i2c_transfer(state->i2c_adap, msg, 2);
142 state->cfg->i2c_addr, reg, ret);
151 #define read_reg(state, reg) \
154 int ret = lgdt3305_read_reg(state, reg, &__val); \
160 static int lgdt3305_set_reg_bit(struct lgdt3305_state *state,
168 ret = lgdt3305_read_reg(state, reg, &val);
175 ret = lgdt3305_write_reg(state, reg, val);
185 static int lgdt3305_write_regs(struct lgdt3305_state *state,
193 ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val);
202 static int lgdt3305_soft_reset(struct lgdt3305_state *state)
208 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 0);
213 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 1);
218 static inline int lgdt3305_mpeg_mode(struct lgdt3305_state *state,
222 return lgdt3305_set_reg_bit(state, LGDT3305_TP_CTRL_1, 5, mode);
225 static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state)
229 enum lgdt3305_tp_clock_edge edge = state->cfg->tpclk_edge;
230 enum lgdt3305_tp_clock_mode mode = state->cfg->tpclk_mode;
231 enum lgdt3305_tp_valid_polarity valid = state->cfg->tpvalid_polarity;
235 ret = lgdt3305_read_reg(state, LGDT3305_TP_CTRL_1, &val);
248 ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val);
252 ret = lgdt3305_soft_reset(state);
257 static int lgdt3305_set_modulation(struct lgdt3305_state *state,
265 ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_1, &opermode);
284 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_1, opermode);
289 static int lgdt3305_set_filter_extension(struct lgdt3305_state *state,
307 return lgdt3305_set_reg_bit(state, 0x043f, 2, val);
312 static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state,
333 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_1, agc_ref >> 8);
334 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff);
339 static int lgdt3305_rfagc_loop(struct lgdt3305_state *state,
356 if (state->cfg->demod_chip == LGDT3304)
358 else /* (state->cfg->demod_chip == LGDT3305) */
365 if (state->cfg->rf_agc_loop) {
369 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_1,
371 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_2,
374 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_1,
376 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_2,
382 lgdt3305_write_reg(state, LGDT3305_IFBW_1, ifbw >> 8);
383 lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff);
389 static int lgdt3305_agc_setup(struct lgdt3305_state *state,
411 switch (state->cfg->demod_chip) {
413 lgdt3305_write_reg(state, 0x0314, 0xe1 | lockdten << 1);
414 lgdt3305_set_reg_bit(state, 0x030e, 2, acqen);
417 lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1);
418 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 2, acqen);
424 return lgdt3305_rfagc_loop(state, p);
427 static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state,
434 if (state->cfg->usref_8vsb)
435 usref = state->cfg->usref_8vsb;
438 if (state->cfg->usref_qam64)
439 usref = state->cfg->usref_qam64;
442 if (state->cfg->usref_qam256)
443 usref = state->cfg->usref_qam256;
452 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 3, 1);
454 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_1,
456 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_2,
464 static int lgdt3305_spectral_inversion(struct lgdt3305_state *state,
474 ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7,
479 ret = lgdt3305_write_reg(state, LGDT3305_FEC_BLOCK_CTRL,
488 static int lgdt3305_set_if(struct lgdt3305_state *state,
497 if_freq_khz = state->cfg->vsb_if_khz;
501 if_freq_khz = state->cfg->qam_if_khz;
529 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, nco1);
530 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, nco2);
531 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, nco3);
532 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, nco4);
544 struct lgdt3305_state *state = fe->demodulator_priv;
546 if (state->cfg->deny_i2c_rptr)
551 return lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_2, 5,
557 struct lgdt3305_state *state = fe->demodulator_priv;
562 gen_ctrl_3 = read_reg(state, LGDT3305_GEN_CTRL_3);
563 gen_ctrl_4 = read_reg(state, LGDT3305_GEN_CTRL_4);
577 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_3, gen_ctrl_3);
578 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_4, gen_ctrl_4);
585 struct lgdt3305_state *state = fe->demodulator_priv;
649 switch (state->cfg->demod_chip) {
651 ret = lgdt3305_write_regs(state, lgdt3304_init_data,
655 ret = lgdt3305_write_regs(state, lgdt3305_init_data,
664 ret = lgdt3305_soft_reset(state);
672 struct lgdt3305_state *state = fe->demodulator_priv;
683 state->current_frequency = p->frequency;
686 ret = lgdt3305_set_modulation(state, p);
690 ret = lgdt3305_passband_digital_agc(state, p);
694 ret = lgdt3305_agc_setup(state, p);
701 lgdt3305_write_reg(state, 0x030d, 0x00);
702 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f);
703 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, 0x0c);
704 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, 0xac);
705 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, 0xba);
709 lgdt3305_write_reg(state, 0x030d, 0x14);
710 ret = lgdt3305_set_if(state, p);
719 ret = lgdt3305_spectral_inversion(state, p,
720 state->cfg->spectral_inversion
725 state->current_modulation = p->modulation;
727 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
732 ret = lgdt3305_mpeg_mode_polarity(state);
740 struct lgdt3305_state *state = fe->demodulator_priv;
751 state->current_frequency = p->frequency;
754 ret = lgdt3305_set_modulation(state, p);
758 ret = lgdt3305_passband_digital_agc(state, p);
761 ret = lgdt3305_set_agc_power_ref(state, p);
764 ret = lgdt3305_agc_setup(state, p);
769 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f);
772 ret = lgdt3305_set_reg_bit(state, LGDT3305_CR_CTR_FREQ_1, 6, 1);
776 ret = lgdt3305_set_if(state, p);
779 ret = lgdt3305_spectral_inversion(state, p,
780 state->cfg->spectral_inversion
785 ret = lgdt3305_set_filter_extension(state, p);
789 state->current_modulation = p->modulation;
791 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
796 ret = lgdt3305_mpeg_mode_polarity(state);
804 struct lgdt3305_state *state = fe->demodulator_priv;
808 p->modulation = state->current_modulation;
809 p->frequency = state->current_frequency;
815 static int lgdt3305_read_cr_lock_status(struct lgdt3305_state *state,
824 ret = lgdt3305_read_reg(state, LGDT3305_CR_LOCK_STATUS, &val);
828 switch (state->current_modulation) {
866 static int lgdt3305_read_fec_lock_status(struct lgdt3305_state *state,
874 switch (state->current_modulation) {
877 ret = lgdt3305_read_reg(state,
903 struct lgdt3305_state *state = fe->demodulator_priv;
910 ret = lgdt3305_read_reg(state, LGDT3305_GEN_STATUS, &val);
927 ret = lgdt3305_read_cr_lock_status(state, &cr_lock);
940 switch (state->current_modulation) {
944 if (((LGDT3304 == state->cfg->demod_chip)) && (cr_lock))
947 ret = lgdt3305_read_fec_lock_status(state, &fec_lock);
985 struct lgdt3305_state *state = fe->demodulator_priv;
989 switch (state->current_modulation) {
994 noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) |
995 (read_reg(state, LGDT3305_PT_MSE_2) << 8) |
996 (read_reg(state, LGDT3305_PT_MSE_3) & 0xff);
1001 noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) |
1002 (read_reg(state, LGDT3305_EQ_MSE_2) << 8) |
1003 (read_reg(state, LGDT3305_EQ_MSE_3) & 0xff);
1009 noise = (read_reg(state, LGDT3305_CR_MSE_1) << 8) |
1010 (read_reg(state, LGDT3305_CR_MSE_2) & 0xff);
1012 c = (state->current_modulation == QAM_64) ?
1019 state->snr = calculate_snr(noise, c);
1021 *snr = (state->snr / ((1 << 24) / 10));
1023 state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
1038 struct lgdt3305_state *state = fe->demodulator_priv;
1047 /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
1049 if (state->snr >= 8960 * 0x10000)
1052 *strength = state->snr / 8960;
1067 struct lgdt3305_state *state = fe->demodulator_priv;
1070 (read_reg(state, LGDT3305_FEC_PKT_ERR_1) << 8) |
1071 (read_reg(state, LGDT3305_FEC_PKT_ERR_2) & 0xff);
1087 struct lgdt3305_state *state = fe->demodulator_priv;
1089 kfree(state);
1098 struct lgdt3305_state *state = NULL;
1106 state = kzalloc(sizeof(struct lgdt3305_state), GFP_KERNEL);
1107 if (state == NULL)
1110 state->cfg = config;
1111 state->i2c_adap = i2c_adap;
1115 memcpy(&state->frontend.ops, &lgdt3304_ops,
1119 memcpy(&state->frontend.ops, &lgdt3305_ops,
1125 state->frontend.demodulator_priv = state;
1128 ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_2, &val);
1131 ret = lgdt3305_write_reg(state, 0x0808, 0x80);
1134 ret = lgdt3305_read_reg(state, 0x0808, &val);
1137 ret = lgdt3305_write_reg(state, 0x0808, 0x00);
1141 state->current_frequency = -1;
1142 state->current_modulation = -1;
1144 return &state->frontend;
1148 kfree(state);