Lines Matching refs:val
53 static int lg216x_write_reg(struct lg216x_state *state, u16 reg, u8 val)
56 u8 buf[] = { reg >> 8, reg & 0xff, val };
62 lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
77 static int lg216x_read_reg(struct lg216x_state *state, u16 reg, u8 *val)
85 .flags = I2C_M_RD, .buf = val, .len = 1 },
105 u8 val;
116 ret = lg216x_write_reg(state, regs[i].reg, regs[i].val);
126 u8 val;
131 ret = lg216x_read_reg(state, reg, &val);
135 val &= ~(1 << bit);
136 val |= (onoff & 1) << bit;
138 ret = lg216x_write_reg(state, reg, val);
189 { .reg = 0x0015, .val = 0xe6 },
191 { .reg = 0x0015, .val = 0xf7 },
192 { .reg = 0x001b, .val = 0x52 },
193 { .reg = 0x0208, .val = 0x00 },
194 { .reg = 0x0209, .val = 0x82 },
195 { .reg = 0x0210, .val = 0xf9 },
196 { .reg = 0x020a, .val = 0x00 },
197 { .reg = 0x020b, .val = 0x82 },
198 { .reg = 0x020d, .val = 0x28 },
199 { .reg = 0x020f, .val = 0x14 },
204 { .reg = 0x0000, .val = 0x41 },
205 { .reg = 0x0001, .val = 0xfb },
206 { .reg = 0x0216, .val = 0x00 },
207 { .reg = 0x0219, .val = 0x00 },
208 { .reg = 0x021b, .val = 0x55 },
209 { .reg = 0x0606, .val = 0x0a },
238 u8 val;
243 ret = lg216x_read_reg(state, 0x0132, &val);
247 val &= 0xfb;
248 val |= (0 == state->cfg->if_khz) ? 0x04 : 0x00;
250 ret = lg216x_write_reg(state, 0x0132, val);
263 u8 val;
266 ret = lg216x_read_reg(state, 0x0100, &val);
270 val &= 0xf3;
271 val |= (if_agc_fix) ? 0x08 : 0x00;
272 val |= (rf_agc_fix) ? 0x04 : 0x00;
274 ret = lg216x_write_reg(state, 0x0100, val);
284 u8 val;
287 ret = lg216x_read_reg(state, 0x0100, &val);
291 val &= 0xcf;
292 val |= (if_agc_freeze) ? 0x20 : 0x00;
293 val |= (rf_agc_freeze) ? 0x10 : 0x00;
295 ret = lg216x_write_reg(state, 0x0100, val);
305 u8 val;
308 ret = lg216x_read_reg(state, 0x0100, &val);
312 val &= 0xfc;
313 val |= (if_agc_polarity) ? 0x02 : 0x00;
314 val |= (rf_agc_polarity) ? 0x01 : 0x00;
316 ret = lg216x_write_reg(state, 0x0100, val);
325 u8 val;
328 ret = lg216x_read_reg(state, 0x0008, &val);
332 val &= 0xfe;
333 val |= (polarity) ? 0x01 : 0x00;
335 ret = lg216x_write_reg(state, 0x0008, val);
344 u8 val;
347 ret = lg216x_read_reg(state, 0x0132, &val);
351 val &= 0xfd;
352 val |= (inverted) ? 0x02 : 0x00;
354 ret = lg216x_write_reg(state, 0x0132, val);
362 u8 val;
365 ret = lg216x_read_reg(state, 0x0007, &val);
369 val &= 0xbf;
370 val |= (onoff) ? 0x40 : 0x00;
372 ret = lg216x_write_reg(state, 0x0007, val);
395 u8 val;
407 ret = lg216x_read_reg(state, reg, &val);
411 val &= 0xfe;
412 val |= (id) ? 0x01 : 0x00;
414 ret = lg216x_write_reg(state, reg, val);
422 u8 val;
425 ret = lg216x_read_reg(state, 0x0014, &val);
429 val &= 0xf3;
430 val |= (state->cfg->spi_clock << 2);
432 ret = lg216x_write_reg(state, 0x0014, val);
440 u8 val;
443 ret = lg216x_read_reg(state, 0x0014, &val);
447 val &= ~0x07;
448 val |= state->cfg->output_if; /* FIXME: needs sanity check */
450 ret = lg216x_write_reg(state, 0x0014, val);
496 u8 val;
501 ret = lg216x_read_reg(state, 0x0128, &val);
505 *ficver = (val >> 3) & 0x1f;
513 u8 val;
518 ret = lg216x_read_reg(state, 0x0123, &val);
522 *id = val & 0x7f;
530 u8 val;
535 ret = lg216x_read_reg(state, 0x0124, &val);
539 *nog = ((val >> 4) & 0x07) + 1;
546 u8 val;
551 ret = lg216x_read_reg(state, 0x0125, &val);
555 *tnog = val & 0x1f;
562 u8 val;
567 ret = lg216x_read_reg(state, 0x0124, &val);
571 *sgn = val & 0x0f;
578 u8 val;
583 ret = lg216x_read_reg(state, 0x0125, &val);
587 *prc = ((val >> 5) & 0x07) + 1;
597 u8 val;
602 ret = lg216x_read_reg(state, 0x0410, &val);
605 ret = lg216x_read_reg(state, 0x0513, &val);
613 switch ((val >> 4) & 0x03) {
637 u8 val;
642 ret = lg216x_read_reg(state, 0x0400, &val);
645 ret = lg216x_read_reg(state, 0x0500, &val);
653 val &= 0x01;
654 *rs_frame_ens = (enum atscmh_rs_frame_ensemble) val;
663 u8 val;
668 ret = lg216x_read_reg(state, 0x0410, &val);
671 ret = lg216x_read_reg(state, 0x0513, &val);
679 *rs_code_pri = (enum atscmh_rs_code_mode) ((val >> 2) & 0x03);
680 *rs_code_sec = (enum atscmh_rs_code_mode) (val & 0x03);
688 u8 val;
693 ret = lg216x_read_reg(state, 0x0315, &val);
696 ret = lg216x_read_reg(state, 0x0511, &val);
704 switch (val & 0x03) {
725 u8 val;
730 ret = lg216x_read_reg(state, 0x0316, &val);
733 ret = lg216x_read_reg(state, 0x0512, &val);
741 switch ((val >> 6) & 0x03) {
753 switch ((val >> 4) & 0x03) {
765 switch ((val >> 2) & 0x03) {
777 switch (val & 0x03) {
1122 u8 val;
1128 ret = lg216x_read_reg(state, 0x011b, &val);
1132 *sync_lock = (val & 0x20) ? 0 : 1;
1133 *acq_lock = (val & 0x40) ? 0 : 1;
1142 u8 val;
1148 ret = lg216x_read_reg(state, 0x0304, &val);
1152 *sync_lock = (val & 0x80) ? 0 : 1;
1154 ret = lg216x_read_reg(state, 0x011b, &val);
1158 *acq_lock = (val & 0x40) ? 0 : 1;