Lines Matching refs:l64781_writereg
40 static int l64781_writereg (struct l64781_state* state, u8 reg, u8 data)
70 l64781_writereg (state, 0x2a, 0x00);
71 l64781_writereg (state, 0x2a, 0x01);
78 l64781_writereg (state, 0x2a, 0x02);
86 l64781_writereg (state, 0x07, 0x9e); /* stall AFC */
87 l64781_writereg (state, 0x08, 0); /* AFC INIT FREQ */
88 l64781_writereg (state, 0x09, 0);
89 l64781_writereg (state, 0x0a, 0);
90 l64781_writereg (state, 0x07, 0x8e);
91 l64781_writereg (state, 0x0e, 0); /* AGC gain to zero in beginning */
92 l64781_writereg (state, 0x11, 0x80); /* stall TIM */
93 l64781_writereg (state, 0x10, 0); /* TIM_OFFSET_LSB */
94 l64781_writereg (state, 0x12, 0);
95 l64781_writereg (state, 0x13, 0);
96 l64781_writereg (state, 0x11, 0x00);
205 l64781_writereg (state, 0x04, val0x04);
206 l64781_writereg (state, 0x05, val0x05);
207 l64781_writereg (state, 0x06, val0x06);
212 l64781_writereg (state, 0x15,
214 l64781_writereg (state, 0x16, init_freq & 0xff);
215 l64781_writereg (state, 0x17, (init_freq >> 8) & 0xff);
216 l64781_writereg (state, 0x18, (init_freq >> 16) & 0xff);
218 l64781_writereg (state, 0x1b, spi_bias & 0xff);
219 l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff);
220 l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) |
223 l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff);
224 l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f);
426 return l64781_writereg (state, 0x3e, 0x5a);
436 l64781_writereg (state, 0x3e, 0xa5);
439 l64781_writereg (state, 0x2a, 0x04);
440 l64781_writereg (state, 0x2a, 0x00);
444 l64781_writereg (state, 0x07, 0x8e);
447 l64781_writereg (state, 0x0b, 0x81);
450 l64781_writereg (state, 0x0c, 0x84);
453 l64781_writereg (state, 0x0d, 0x8c);
458 /*l64781_writereg (state, 0x19, 0x92);*/
461 l64781_writereg (state, 0x1e, 0x09);
533 l64781_writereg (state, 0x3e, 0x5a);
542 l64781_writereg (state, 0x3e, 0xa5);
557 l64781_writereg (state, 0x3e, reg0x3e); /* restore reg 0x3e */