Lines Matching refs:status
228 int status;
239 status = drxk_i2c_transfer(state, &msg, 1);
240 if (status >= 0 && status != 1)
241 status = -EIO;
243 if (status < 0)
246 return status;
252 int status;
260 status = drxk_i2c_transfer(state, msgs, 2);
261 if (status != 2) {
264 if (status >= 0)
265 status = -EIO;
268 return status;
285 int status;
303 status = i2c_read(state, adr, mm1, len, mm2, 2);
304 if (status < 0)
305 return status;
319 int status;
337 status = i2c_read(state, adr, mm1, len, mm2, 4);
338 if (status < 0)
339 return status;
415 int status = 0, blk_size = block_size;
451 status = i2c_write(state, state->demod_address,
453 if (status < 0) {
462 return status;
471 int status;
477 status = i2c_read1(state, state->demod_address, &data);
478 if (status < 0) {
481 status = i2c_write(state, state->demod_address,
485 if (status < 0)
487 status = i2c_read1(state, state->demod_address,
489 } while (status < 0 &&
491 if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)
496 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
497 if (status < 0)
499 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
500 if (status < 0)
503 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
504 if (status < 0)
510 if (status < 0)
511 pr_err("Error %d on %s\n", status, __func__);
513 return status;
754 int status = 0;
761 status = write16(state, SCU_RAM_GPIO__A,
763 if (status < 0)
766 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
767 if (status < 0)
769 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
770 if (status < 0)
772 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
773 if (status < 0)
775 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
776 if (status < 0)
778 status = write16(state, SIO_TOP_COMM_KEY__A, key);
780 if (status < 0)
781 pr_err("Error %d on %s\n", status, __func__);
782 return status;
789 int status;
796 status = write16(state, SCU_RAM_GPIO__A,
798 if (status < 0)
800 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
801 if (status < 0)
803 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
804 if (status < 0)
806 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
807 if (status < 0)
834 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
835 if (status < 0)
838 pr_info("status = 0x%08x\n", sio_top_jtagid_lo);
856 status = -EINVAL;
968 status = -EINVAL;
978 if (status < 0)
979 pr_err("Error %d on %s\n", status, __func__);
982 return status;
987 int status;
993 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
994 if (status < 0)
1012 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1014 } while ((status < 0 || wait_cmd) && (retry_count < DRXK_MAX_RETRIES));
1015 if (status < 0)
1017 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
1020 if (status < 0)
1021 pr_err("Error %d on %s\n", status, __func__);
1023 return status;
1028 int status;
1034 status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
1036 if (status < 0)
1038 status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
1040 if (status < 0)
1042 status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
1044 if (status < 0)
1046 status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
1048 if (status < 0)
1050 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
1052 if (status < 0)
1054 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
1056 if (status < 0)
1058 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);
1059 if (status < 0)
1065 if (status < 0)
1066 pr_err("Error %d on %s\n", status, __func__);
1067 return status;
1084 int status;
1094 status = write16(state, SCU_RAM_GPIO__A,
1096 if (status < 0)
1100 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1101 if (status < 0)
1106 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1107 if (status < 0)
1109 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1110 if (status < 0)
1112 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1113 if (status < 0)
1115 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1116 if (status < 0)
1118 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1119 if (status < 0)
1121 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1122 if (status < 0)
1124 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1125 if (status < 0)
1127 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1128 if (status < 0)
1130 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1131 if (status < 0)
1133 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1134 if (status < 0)
1136 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1137 if (status < 0)
1139 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1140 if (status < 0)
1151 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
1152 if (status < 0)
1158 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1159 if (status < 0)
1161 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1162 if (status < 0)
1167 status = write16(state, SIO_PDR_MD1_CFG__A,
1169 if (status < 0)
1171 status = write16(state, SIO_PDR_MD2_CFG__A,
1173 if (status < 0)
1175 status = write16(state, SIO_PDR_MD3_CFG__A,
1177 if (status < 0)
1179 status = write16(state, SIO_PDR_MD4_CFG__A,
1181 if (status < 0)
1183 status = write16(state, SIO_PDR_MD5_CFG__A,
1185 if (status < 0)
1187 status = write16(state, SIO_PDR_MD6_CFG__A,
1189 if (status < 0)
1191 status = write16(state, SIO_PDR_MD7_CFG__A,
1193 if (status < 0)
1200 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1201 if (status < 0)
1203 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1204 if (status < 0)
1206 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1207 if (status < 0)
1209 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1210 if (status < 0)
1212 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1213 if (status < 0)
1215 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1216 if (status < 0)
1218 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1219 if (status < 0)
1222 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
1223 if (status < 0)
1225 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
1226 if (status < 0)
1230 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1231 if (status < 0)
1234 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1236 if (status < 0)
1237 pr_err("Error %d on %s\n", status, __func__);
1238 return status;
1252 int status;
1257 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1258 if (status < 0)
1260 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
1261 if (status < 0)
1263 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
1264 if (status < 0)
1266 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1267 if (status < 0)
1273 status = read16(state, SIO_BL_STATUS__A, &bl_status);
1274 if (status < 0)
1281 status = -EINVAL;
1285 if (status < 0)
1286 pr_err("Error %d on %s\n", status, __func__);
1289 return status;
1302 int status = 0;
1346 status = write_block(state, address, block_size, p_src);
1347 if (status < 0) {
1348 pr_err("Error %d while loading firmware\n", status);
1354 return status;
1359 int status;
1372 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1373 if (status >= 0 && data == desired_status) {
1374 /* tokenring already has correct status */
1375 return status;
1378 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
1382 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1383 if ((status >= 0 && data == desired_status)
1392 return status;
1397 int status = 0;
1404 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1405 if (status < 0)
1408 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1409 if (status < 0)
1413 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
1414 if (status < 0)
1417 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
1420 if (status < 0)
1421 pr_err("Error %d on %s\n", status, __func__);
1423 return status;
1434 int status = -EINVAL;
1445 pr_err("Error %d on %s\n", status, __func__);
1446 return status;
1468 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
1469 if (status < 0)
1474 status = -EIO;
1483 status = read16(state, SCU_RAM_PARAM_0__A - ii,
1485 if (status < 0)
1514 status = -EINVAL;
1519 if (status < 0)
1520 pr_err("Error %d on %s\n", status, __func__);
1523 return status;
1529 int status;
1534 status = read16(state, IQM_AF_STDBY__A, &data);
1535 if (status < 0)
1552 status = write16(state, IQM_AF_STDBY__A, data);
1555 if (status < 0)
1556 pr_err("Error %d on %s\n", status, __func__);
1557 return status;
1562 int status = 0;
1598 status = power_up_device(state);
1599 if (status < 0)
1601 status = dvbt_enable_ofdm_token_ring(state, true);
1602 if (status < 0)
1620 status = mpegts_stop(state);
1621 if (status < 0)
1623 status = power_down_dvbt(state, false);
1624 if (status < 0)
1629 status = mpegts_stop(state);
1630 if (status < 0)
1632 status = power_down_qam(state);
1633 if (status < 0)
1639 status = dvbt_enable_ofdm_token_ring(state, false);
1640 if (status < 0)
1642 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
1643 if (status < 0)
1645 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1646 if (status < 0)
1652 status = hi_cfg_command(state);
1653 if (status < 0)
1660 if (status < 0)
1661 pr_err("Error %d on %s\n", status, __func__);
1663 return status;
1671 int status;
1675 status = read16(state, SCU_COMM_EXEC__A, &data);
1676 if (status < 0)
1680 status = scu_command(state,
1684 if (status < 0)
1687 status = scu_command(state,
1691 if (status < 0)
1696 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1697 if (status < 0)
1699 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1700 if (status < 0)
1702 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1703 if (status < 0)
1707 status = set_iqm_af(state, false);
1708 if (status < 0)
1713 status = ctrl_power_mode(state, &power_mode);
1714 if (status < 0)
1718 if (status < 0)
1719 pr_err("Error %d on %s\n", status, __func__);
1720 return status;
1726 int status = 0;
1736 status = write16(state, SCU_RAM_GPIO__A,
1738 if (status < 0)
1750 status = mpegts_stop(state);
1751 if (status < 0)
1753 status = power_down_dvbt(state, true);
1754 if (status < 0)
1760 status = mpegts_stop(state);
1761 if (status < 0)
1763 status = power_down_qam(state);
1764 if (status < 0)
1770 status = -EINVAL;
1781 status = set_dvbt_standard(state, o_mode);
1782 if (status < 0)
1790 status = set_qam_standard(state, o_mode);
1791 if (status < 0)
1796 status = -EINVAL;
1799 if (status < 0)
1800 pr_err("Error %d on %s\n", status, __func__);
1801 return status;
1807 int status = -EINVAL;
1828 status = set_qam(state, i_freqk_hz, offsetk_hz);
1829 if (status < 0)
1835 status = mpegts_stop(state);
1836 if (status < 0)
1838 status = set_dvbt(state, i_freqk_hz, offsetk_hz);
1839 if (status < 0)
1841 status = dvbt_start(state);
1842 if (status < 0)
1850 if (status < 0)
1851 pr_err("Error %d on %s\n", status, __func__);
1852 return status;
1865 int status = -EINVAL;
1879 status = get_qam_lock_status(state, p_lock_status);
1882 status = get_dvbt_lock_status(state, p_lock_status);
1890 if (status < 0)
1891 pr_err("Error %d on %s\n", status, __func__);
1892 return status;
1897 int status;
1902 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1903 if (status < 0)
1906 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1907 if (status < 0)
1909 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1911 if (status < 0)
1912 pr_err("Error %d on %s\n", status, __func__);
1913 return status;
1918 int status;
1923 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1924 if (status < 0)
1926 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1927 if (status < 0)
1929 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1930 if (status < 0)
1932 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1933 if (status < 0)
1935 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1936 if (status < 0)
1938 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1939 if (status < 0)
1941 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1942 if (status < 0)
1944 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1945 if (status < 0)
1949 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1950 if (status < 0)
1952 status = write16(state, FEC_OC_SNC_LWM__A, 2);
1953 if (status < 0)
1955 status = write16(state, FEC_OC_SNC_HWM__A, 12);
1957 if (status < 0)
1958 pr_err("Error %d on %s\n", status, __func__);
1960 return status;
1966 int status;
1983 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
1984 if (status < 0)
1986 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
1987 if (status < 0)
2022 status = -EINVAL;
2024 if (status < 0)
2066 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
2067 if (status < 0)
2069 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
2070 if (status < 0)
2072 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
2073 if (status < 0)
2075 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
2076 if (status < 0)
2078 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
2079 if (status < 0)
2081 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
2082 if (status < 0)
2086 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
2087 if (status < 0)
2089 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
2091 if (status < 0)
2093 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
2095 if (status < 0)
2096 pr_err("Error %d on %s\n", status, __func__);
2097 return status;
2138 int status = -EINVAL;
2150 status = read16(state, IQM_AF_STDBY__A, &data);
2151 if (status < 0)
2154 status = write16(state, IQM_AF_STDBY__A, data);
2155 if (status < 0)
2157 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2158 if (status < 0)
2169 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2170 if (status < 0)
2174 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2175 if (status < 0)
2183 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2184 if (status < 0)
2194 status = -EINVAL;
2200 status = write16(state,
2203 if (status < 0)
2208 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
2210 if (status < 0)
2214 status = write16(state, SCU_RAM_AGC_RF_MAX__A,
2216 if (status < 0)
2223 status = read16(state, IQM_AF_STDBY__A, &data);
2224 if (status < 0)
2227 status = write16(state, IQM_AF_STDBY__A, data);
2228 if (status < 0)
2232 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2233 if (status < 0)
2240 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2241 if (status < 0)
2245 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2246 if (status < 0)
2250 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
2252 if (status < 0)
2258 status = read16(state, IQM_AF_STDBY__A, &data);
2259 if (status < 0)
2262 status = write16(state, IQM_AF_STDBY__A, data);
2263 if (status < 0)
2267 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2268 if (status < 0)
2271 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2272 if (status < 0)
2277 status = -EINVAL;
2281 if (status < 0)
2282 pr_err("Error %d on %s\n", status, __func__);
2283 return status;
2292 int status = 0;
2301 status = read16(state, IQM_AF_STDBY__A, &data);
2302 if (status < 0)
2305 status = write16(state, IQM_AF_STDBY__A, data);
2306 if (status < 0)
2309 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2310 if (status < 0)
2321 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2322 if (status < 0)
2326 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2327 if (status < 0)
2334 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2335 if (status < 0)
2345 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2347 if (status < 0)
2354 status = read16(state, IQM_AF_STDBY__A, &data);
2355 if (status < 0)
2358 status = write16(state, IQM_AF_STDBY__A, data);
2359 if (status < 0)
2362 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2363 if (status < 0)
2374 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2375 if (status < 0)
2379 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2381 if (status < 0)
2388 status = read16(state, IQM_AF_STDBY__A, &data);
2389 if (status < 0)
2392 status = write16(state, IQM_AF_STDBY__A, data);
2393 if (status < 0)
2397 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2398 if (status < 0)
2401 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2402 if (status < 0)
2409 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
2411 if (status < 0)
2412 pr_err("Error %d on %s\n", status, __func__);
2413 return status;
2419 int status = 0;
2431 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
2432 if (status < 0) {
2433 pr_err("Error %d on %s\n", status, __func__);
2462 return status;
2468 int status;
2485 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
2487 if (status < 0)
2489 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
2491 if (status < 0)
2493 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
2495 if (status < 0)
2497 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
2499 if (status < 0)
2507 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data);
2508 if (status < 0)
2516 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
2518 if (status < 0)
2564 if (status < 0)
2565 pr_err("Error %d on %s\n", status, __func__);
2566 return status;
2590 int status = 0;
2621 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2622 if (status < 0)
2624 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2626 if (status < 0)
2630 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2632 if (status < 0)
2656 int status = 0;
2666 status = get_qam_signal_to_noise(state, &signal_to_noise);
2667 if (status < 0)
2698 return status;
2733 int status = -EINVAL;
2745 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
2747 if (status < 0)
2750 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2752 if (status < 0)
2755 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2757 if (status < 0)
2761 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);
2764 if (status < 0)
2765 pr_err("Error %d on %s\n", status, __func__);
2766 return status;
2772 int status = -EINVAL;
2780 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
2782 if (status < 0)
2783 pr_err("Error %d on %s\n", status, __func__);
2784 return status;
2793 int status;
2799 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2800 if (status < 0)
2802 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2803 if (status < 0)
2805 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2806 if (status < 0)
2808 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
2809 if (status < 0)
2811 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
2812 if (status < 0)
2814 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2815 if (status < 0)
2820 status = read16(state, SIO_BL_STATUS__A, &bl_status);
2821 if (status < 0)
2826 status = -EINVAL;
2830 if (status < 0)
2831 pr_err("Error %d on %s\n", status, __func__);
2834 return status;
2841 int status;
2846 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2847 if (status < 0)
2849 status = write16(state, IQM_AF_START_LOCK__A, 1);
2850 if (status < 0)
2854 status = read16(state, IQM_AF_PHASE0__A, &data);
2855 if (status < 0)
2859 status = read16(state, IQM_AF_PHASE1__A, &data);
2860 if (status < 0)
2864 status = read16(state, IQM_AF_PHASE2__A, &data);
2865 if (status < 0)
2871 if (status < 0)
2872 pr_err("Error %d on %s\n", status, __func__);
2873 return status;
2879 int status;
2883 status = adc_sync_measurement(state, &count);
2884 if (status < 0)
2891 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
2892 if (status < 0)
2904 status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
2905 if (status < 0)
2907 status = adc_sync_measurement(state, &count);
2908 if (status < 0)
2913 status = -EINVAL;
2915 if (status < 0)
2916 pr_err("Error %d on %s\n", status, __func__);
2917 return status;
2930 int status;
2979 status = write32(state, IQM_FS_RATE_OFS_LO__A,
2981 if (status < 0)
2982 pr_err("Error %d on %s\n", status, __func__);
2983 return status;
3005 int status = 0;
3038 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3040 if (status < 0)
3043 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
3044 if (status < 0)
3046 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
3047 if (status < 0)
3049 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
3050 if (status < 0)
3052 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
3053 if (status < 0)
3055 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
3057 if (status < 0)
3059 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
3061 if (status < 0)
3063 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3064 if (status < 0)
3066 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3067 if (status < 0)
3069 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3070 if (status < 0)
3072 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3073 if (status < 0)
3075 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
3076 if (status < 0)
3078 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
3079 if (status < 0)
3082 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
3084 if (status < 0)
3086 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
3088 if (status < 0)
3090 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
3091 if (status < 0)
3094 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3095 if (status < 0)
3097 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3098 if (status < 0)
3100 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3101 if (status < 0)
3104 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3105 if (status < 0)
3107 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
3108 if (status < 0)
3110 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
3111 if (status < 0)
3113 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
3114 if (status < 0)
3116 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
3117 if (status < 0)
3119 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3120 if (status < 0)
3122 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3123 if (status < 0)
3125 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3126 if (status < 0)
3128 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3129 if (status < 0)
3131 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3132 if (status < 0)
3134 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3135 if (status < 0)
3137 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3138 if (status < 0)
3140 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3141 if (status < 0)
3143 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3144 if (status < 0)
3146 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3147 if (status < 0)
3149 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3150 if (status < 0)
3152 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3153 if (status < 0)
3155 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3156 if (status < 0)
3158 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3159 if (status < 0)
3163 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3164 if (status < 0)
3173 status = write16(state, SCU_RAM_AGC_KI__A, data);
3175 if (status < 0)
3176 pr_err("Error %d on %s\n", status, __func__);
3177 return status;
3182 int status;
3186 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3188 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
3190 if (status < 0)
3191 pr_err("Error %d on %s\n", status, __func__);
3192 return status;
3204 int status;
3207 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
3210 status = -EINVAL;
3212 if (status < 0)
3219 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3222 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3231 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3232 if (status < 0)
3241 status = 0;
3250 status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3254 status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3259 status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3263 status = -EINVAL;
3265 if (status < 0)
3272 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3275 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3279 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
3282 status = -EINVAL;
3284 if (status < 0)
3296 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3307 status = -EINVAL;
3311 if (status < 0)
3312 pr_err("Error %d on %s\n", status, __func__);
3313 return status;
3319 int status;
3322 status = ctrl_power_mode(state, &power_mode);
3323 if (status < 0)
3324 pr_err("Error %d on %s\n", status, __func__);
3325 return status;
3330 int status;
3334 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3336 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3337 if (status < 0)
3338 pr_err("Error %d on %s\n", status, __func__);
3339 return status;
3346 int status;
3351 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3355 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3357 if (status < 0)
3358 pr_err("Error %d on %s\n", status, __func__);
3360 return status;
3367 int status;
3370 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3371 if (status < 0)
3391 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3393 if (status < 0)
3394 pr_err("Error %d on %s\n", status, __func__);
3395 return status;
3401 int status = -EINVAL;
3413 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3416 if (status < 0)
3417 pr_err("Error %d on %s\n", status, __func__);
3418 return status;
3433 int status;
3441 status = dvbt_ctrl_set_inc_enable(state, &setincenable);
3442 if (status < 0)
3444 status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
3445 if (status < 0)
3447 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
3448 if (status < 0)
3450 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
3451 if (status < 0)
3453 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
3456 if (status < 0)
3457 pr_err("Error %d on %s\n", status, __func__);
3458 return status;
3476 int status;
3484 status = scu_command(state,
3488 if (status < 0)
3492 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3495 if (status < 0)
3499 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3500 if (status < 0)
3502 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3503 if (status < 0)
3505 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3506 if (status < 0)
3511 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3512 if (status < 0)
3515 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3516 if (status < 0)
3519 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3520 if (status < 0)
3523 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3524 if (status < 0)
3526 status = set_iqm_af(state, true);
3527 if (status < 0)
3530 status = write16(state, IQM_AF_AGC_RF__A, 0);
3531 if (status < 0)
3535 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3536 if (status < 0)
3538 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3539 if (status < 0)
3541 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3542 if (status < 0)
3545 status = write16(state, IQM_RC_STRETCH__A, 16);
3546 if (status < 0)
3548 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3549 if (status < 0)
3551 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3552 if (status < 0)
3554 status = write16(state, IQM_CF_SCALE__A, 1600);
3555 if (status < 0)
3557 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3558 if (status < 0)
3562 status = write16(state, IQM_AF_CLP_TH__A, 448);
3563 if (status < 0)
3565 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3566 if (status < 0)
3569 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
3571 if (status < 0)
3574 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3575 if (status < 0)
3577 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3578 if (status < 0)
3581 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3582 if (status < 0)
3584 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3585 if (status < 0)
3589 status = adc_synchronization(state);
3590 if (status < 0)
3592 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
3593 if (status < 0)
3597 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3598 if (status < 0)
3601 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
3602 if (status < 0)
3604 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
3605 if (status < 0)
3609 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3610 if (status < 0)
3613 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3614 if (status < 0)
3618 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3619 if (status < 0)
3624 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3626 if (status < 0)
3632 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3633 if (status < 0)
3635 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3636 if (status < 0)
3641 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3642 if (status < 0)
3647 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3648 if (status < 0)
3651 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3652 if (status < 0)
3655 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3656 if (status < 0)
3660 status = mpegts_dto_setup(state, OM_DVBT);
3661 if (status < 0)
3664 status = dvbt_activate_presets(state);
3665 if (status < 0)
3669 if (status < 0)
3670 pr_err("Error %d on %s\n", status, __func__);
3671 return status;
3683 int status;
3690 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
3693 if (status < 0)
3696 status = mpegts_start(state);
3697 if (status < 0)
3699 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3700 if (status < 0)
3703 if (status < 0)
3704 pr_err("Error %d on %s\n", status, __func__);
3705 return status;
3726 int status;
3731 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3734 if (status < 0)
3738 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3739 if (status < 0)
3743 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3744 if (status < 0)
3746 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3747 if (status < 0)
3752 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3753 if (status < 0)
3845 status = -EINVAL;
3851 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3852 if (status < 0)
3898 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3900 if (status < 0)
3903 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3905 if (status < 0)
3907 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3909 if (status < 0)
3911 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3913 if (status < 0)
3915 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3917 if (status < 0)
3922 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3924 if (status < 0)
3927 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3929 if (status < 0)
3931 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3933 if (status < 0)
3935 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3937 if (status < 0)
3939 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3941 if (status < 0)
3946 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3948 if (status < 0)
3951 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3953 if (status < 0)
3955 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3957 if (status < 0)
3959 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3961 if (status < 0)
3963 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3965 if (status < 0)
3969 status = -EINVAL;
4000 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
4001 if (status < 0)
4007 status = dvbt_set_frequency_shift(demod, channel, tuner_offset);
4008 if (status < 0)
4011 status = set_frequency_shifter(state, intermediate_freqk_hz,
4013 if (status < 0)
4019 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4020 if (status < 0)
4024 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4025 if (status < 0)
4027 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4028 if (status < 0)
4032 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
4035 if (status < 0)
4044 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4046 if (status < 0)
4050 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
4052 if (status < 0)
4053 pr_err("Error %d on %s\n", status, __func__);
4055 return status;
4062 * \brief Retrieve lock status .
4064 * \param lockStat Pointer to lock status structure.
4070 int status;
4084 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
4085 if (status < 0)
4090 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
4091 if (status < 0)
4103 if (status < 0)
4104 pr_err("Error %d on %s\n", status, __func__);
4106 return status;
4112 int status;
4115 status = ctrl_power_mode(state, &power_mode);
4116 if (status < 0)
4117 pr_err("Error %d on %s\n", status, __func__);
4119 return status;
4128 int status = 0;
4131 status = read16(state, SCU_COMM_EXEC__A, &data);
4132 if (status < 0)
4140 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4141 if (status < 0)
4143 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
4146 if (status < 0)
4150 status = set_iqm_af(state, false);
4153 if (status < 0)
4154 pr_err("Error %d on %s\n", status, __func__);
4156 return status;
4180 int status = 0;
4208 status = -EINVAL;
4210 if (status < 0)
4224 status = -EINVAL;
4225 if (status < 0)
4233 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
4234 if (status < 0)
4236 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
4238 if (status < 0)
4240 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
4242 if (status < 0)
4243 pr_err("Error %d on %s\n", status, __func__);
4244 return status;
4249 int status = 0;
4254 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4255 if (status < 0)
4257 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4258 if (status < 0)
4260 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4261 if (status < 0)
4263 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4264 if (status < 0)
4266 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4267 if (status < 0)
4269 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4270 if (status < 0)
4273 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4274 if (status < 0)
4276 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4277 if (status < 0)
4279 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4280 if (status < 0)
4282 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4283 if (status < 0)
4285 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4286 if (status < 0)
4288 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4289 if (status < 0)
4292 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4293 if (status < 0)
4295 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4296 if (status < 0)
4298 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4299 if (status < 0)
4303 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4305 if (status < 0)
4309 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4310 if (status < 0)
4312 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4313 if (status < 0)
4315 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4316 if (status < 0)
4318 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4319 if (status < 0)
4321 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4322 if (status < 0)
4324 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4325 if (status < 0)
4327 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4328 if (status < 0)
4330 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4331 if (status < 0)
4334 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4335 if (status < 0)
4337 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4338 if (status < 0)
4340 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4341 if (status < 0)
4343 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4344 if (status < 0)
4346 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4347 if (status < 0)
4349 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4350 if (status < 0)
4352 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4353 if (status < 0)
4355 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4356 if (status < 0)
4358 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4359 if (status < 0)
4361 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4362 if (status < 0)
4364 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4365 if (status < 0)
4367 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4368 if (status < 0)
4374 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4375 if (status < 0)
4377 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4378 if (status < 0)
4380 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4381 if (status < 0)
4383 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4384 if (status < 0)
4386 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4387 if (status < 0)
4389 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4390 if (status < 0)
4393 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4394 if (status < 0)
4396 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4397 if (status < 0)
4399 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4400 if (status < 0)
4406 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4407 if (status < 0)
4409 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4410 if (status < 0)
4412 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4413 if (status < 0)
4415 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4416 if (status < 0)
4418 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4419 if (status < 0)
4421 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4422 if (status < 0)
4424 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4425 if (status < 0)
4429 if (status < 0)
4430 pr_err("Error %d on %s\n", status, __func__);
4431 return status;
4443 int status = 0;
4449 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4450 if (status < 0)
4452 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4453 if (status < 0)
4455 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4456 if (status < 0)
4458 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4459 if (status < 0)
4461 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4462 if (status < 0)
4464 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4465 if (status < 0)
4469 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4470 if (status < 0)
4472 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4473 if (status < 0)
4475 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4476 if (status < 0)
4478 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4479 if (status < 0)
4481 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4482 if (status < 0)
4484 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4485 if (status < 0)
4488 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4489 if (status < 0)
4491 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4492 if (status < 0)
4494 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4495 if (status < 0)
4500 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4502 if (status < 0)
4508 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4509 if (status < 0)
4511 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4512 if (status < 0)
4514 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4515 if (status < 0)
4517 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4518 if (status < 0)
4520 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4521 if (status < 0)
4523 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4524 if (status < 0)
4526 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4527 if (status < 0)
4529 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4530 if (status < 0)
4533 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4534 if (status < 0)
4536 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4537 if (status < 0)
4539 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4540 if (status < 0)
4542 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4543 if (status < 0)
4545 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4546 if (status < 0)
4548 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4549 if (status < 0)
4551 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4552 if (status < 0)
4554 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4555 if (status < 0)
4557 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4558 if (status < 0)
4560 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4561 if (status < 0)
4563 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4564 if (status < 0)
4566 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4567 if (status < 0)
4573 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4574 if (status < 0)
4576 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4577 if (status < 0)
4579 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4580 if (status < 0)
4582 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4583 if (status < 0)
4585 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4586 if (status < 0)
4588 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4589 if (status < 0)
4592 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4593 if (status < 0)
4595 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4596 if (status < 0)
4598 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4599 if (status < 0)
4605 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4606 if (status < 0)
4608 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4609 if (status < 0)
4611 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4612 if (status < 0)
4614 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4615 if (status < 0)
4617 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4618 if (status < 0)
4620 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4621 if (status < 0)
4623 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4625 if (status < 0)
4626 pr_err("Error %d on %s\n", status, __func__);
4627 return status;
4639 int status = 0;
4644 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4645 if (status < 0)
4647 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4648 if (status < 0)
4650 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4651 if (status < 0)
4653 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4654 if (status < 0)
4656 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4657 if (status < 0)
4659 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4660 if (status < 0)
4664 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4665 if (status < 0)
4667 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4668 if (status < 0)
4670 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4671 if (status < 0)
4673 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4674 if (status < 0)
4676 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4677 if (status < 0)
4679 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4680 if (status < 0)
4683 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4684 if (status < 0)
4686 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4687 if (status < 0)
4689 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4690 if (status < 0)
4694 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4696 if (status < 0)
4702 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4703 if (status < 0)
4705 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4706 if (status < 0)
4708 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4709 if (status < 0)
4711 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4712 if (status < 0)
4714 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4715 if (status < 0)
4717 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4718 if (status < 0)
4720 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4721 if (status < 0)
4723 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4724 if (status < 0)
4727 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4728 if (status < 0)
4730 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4731 if (status < 0)
4733 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4734 if (status < 0)
4736 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4737 if (status < 0)
4739 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4740 if (status < 0)
4742 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4743 if (status < 0)
4745 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4746 if (status < 0)
4748 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4749 if (status < 0)
4751 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4752 if (status < 0)
4754 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4755 if (status < 0)
4757 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4758 if (status < 0)
4760 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4761 if (status < 0)
4767 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4768 if (status < 0)
4770 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4771 if (status < 0)
4773 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4774 if (status < 0)
4776 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4777 if (status < 0)
4779 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4780 if (status < 0)
4782 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4783 if (status < 0)
4786 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4787 if (status < 0)
4789 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4790 if (status < 0)
4792 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4793 if (status < 0)
4799 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4800 if (status < 0)
4802 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4803 if (status < 0)
4805 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4806 if (status < 0)
4808 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4809 if (status < 0)
4811 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4812 if (status < 0)
4814 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4815 if (status < 0)
4817 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4819 if (status < 0)
4820 pr_err("Error %d on %s\n", status, __func__);
4822 return status;
4834 int status = 0;
4839 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4840 if (status < 0)
4842 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4843 if (status < 0)
4845 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4846 if (status < 0)
4848 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4849 if (status < 0)
4851 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4852 if (status < 0)
4854 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4855 if (status < 0)
4859 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4860 if (status < 0)
4862 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4863 if (status < 0)
4865 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4866 if (status < 0)
4868 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4869 if (status < 0)
4871 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4872 if (status < 0)
4874 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4875 if (status < 0)
4878 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4879 if (status < 0)
4881 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4882 if (status < 0)
4884 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4885 if (status < 0)
4891 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4893 if (status < 0)
4899 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4900 if (status < 0)
4902 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4903 if (status < 0)
4905 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4906 if (status < 0)
4908 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4909 if (status < 0)
4911 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4912 if (status < 0)
4914 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4915 if (status < 0)
4917 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4918 if (status < 0)
4920 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4921 if (status < 0)
4924 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4925 if (status < 0)
4927 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4928 if (status < 0)
4930 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4931 if (status < 0)
4933 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4934 if (status < 0)
4936 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4937 if (status < 0)
4939 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4940 if (status < 0)
4942 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4943 if (status < 0)
4945 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4946 if (status < 0)
4948 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4949 if (status < 0)
4951 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4952 if (status < 0)
4954 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4955 if (status < 0)
4957 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4958 if (status < 0)
4964 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4965 if (status < 0)
4967 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4968 if (status < 0)
4970 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4971 if (status < 0)
4973 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4974 if (status < 0)
4976 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4977 if (status < 0)
4979 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4980 if (status < 0)
4983 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4984 if (status < 0)
4986 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
4987 if (status < 0)
4990 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
4991 if (status < 0)
4996 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
4997 if (status < 0)
4999 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5000 if (status < 0)
5002 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5003 if (status < 0)
5005 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5006 if (status < 0)
5008 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5009 if (status < 0)
5011 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5012 if (status < 0)
5014 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5016 if (status < 0)
5017 pr_err("Error %d on %s\n", status, __func__);
5019 return status;
5031 int status = 0;
5036 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5037 if (status < 0)
5039 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5040 if (status < 0)
5042 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5043 if (status < 0)
5045 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5046 if (status < 0)
5048 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5049 if (status < 0)
5051 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5052 if (status < 0)
5056 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5057 if (status < 0)
5059 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5060 if (status < 0)
5062 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5063 if (status < 0)
5065 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5066 if (status < 0)
5068 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5069 if (status < 0)
5071 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5072 if (status < 0)
5075 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5076 if (status < 0)
5078 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5079 if (status < 0)
5081 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5082 if (status < 0)
5087 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
5089 if (status < 0)
5095 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5096 if (status < 0)
5098 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5099 if (status < 0)
5101 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5102 if (status < 0)
5104 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5105 if (status < 0)
5107 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5108 if (status < 0)
5110 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5111 if (status < 0)
5113 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5114 if (status < 0)
5116 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5117 if (status < 0)
5120 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5121 if (status < 0)
5123 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5124 if (status < 0)
5126 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5127 if (status < 0)
5129 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5130 if (status < 0)
5132 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5133 if (status < 0)
5135 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5136 if (status < 0)
5138 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5139 if (status < 0)
5141 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5142 if (status < 0)
5144 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5145 if (status < 0)
5147 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5148 if (status < 0)
5150 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5151 if (status < 0)
5153 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5154 if (status < 0)
5160 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5161 if (status < 0)
5163 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5164 if (status < 0)
5166 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5167 if (status < 0)
5169 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5170 if (status < 0)
5172 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5173 if (status < 0)
5175 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5176 if (status < 0)
5179 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5180 if (status < 0)
5182 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5183 if (status < 0)
5185 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5186 if (status < 0)
5192 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5193 if (status < 0)
5195 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5196 if (status < 0)
5198 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5199 if (status < 0)
5201 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5202 if (status < 0)
5204 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5205 if (status < 0)
5207 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5208 if (status < 0)
5210 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5212 if (status < 0)
5213 pr_err("Error %d on %s\n", status, __func__);
5214 return status;
5227 int status;
5232 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5233 if (status < 0)
5236 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5240 if (status < 0)
5241 pr_err("Error %d on %s\n", status, __func__);
5242 return status;
5260 int status;
5272 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5273 if (status < 0)
5282 status = -EINVAL;
5288 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
5289 if (status < 0)
5298 status = -EINVAL;
5306 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
5309 if (status < 0)
5310 pr_err("Error %d on %s\n", status, __func__);
5311 return status;
5317 * \brief Get QAM lock status.
5325 int status;
5330 status = scu_command(state,
5334 if (status < 0)
5335 pr_err("Error %d on %s\n", status, __func__);
5354 return status;
5367 int status;
5382 status = scu_command(state,
5386 if (status < 0)
5389 status = scu_command(state,
5405 status = scu_command(state,
5413 status = -EINVAL;
5417 if (status < 0)
5418 pr_warn("Warning %d on %s\n", status, __func__);
5419 return status;
5425 int status;
5436 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5437 if (status < 0)
5439 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5440 if (status < 0)
5442 status = qam_reset_qam(state);
5443 if (status < 0)
5451 status = qam_set_symbolrate(state);
5452 if (status < 0)
5474 status = -EINVAL;
5477 if (status < 0)
5485 status = qam_demodulator_command(state, qam_demod_param_count);
5492 || (!state->qam_demod_parameter_count && status < 0)) {
5494 status = qam_demodulator_command(state, qam_demod_param_count);
5497 if (status < 0) {
5521 status = set_frequency(channel, tuner_freq_offset));
5522 if (status < 0)
5525 status = set_frequency_shifter(state, intermediate_freqk_hz,
5527 if (status < 0)
5531 status = set_qam_measurement(state, state->m_constellation,
5533 if (status < 0)
5537 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5538 if (status < 0)
5540 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5541 if (status < 0)
5545 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5546 if (status < 0)
5548 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5549 if (status < 0)
5551 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5552 if (status < 0)
5554 status = write16(state, QAM_LC_MODE__A, 7);
5555 if (status < 0)
5558 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5559 if (status < 0)
5561 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5562 if (status < 0)
5564 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5565 if (status < 0)
5567 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5568 if (status < 0)
5570 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5571 if (status < 0)
5573 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5574 if (status < 0)
5576 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5577 if (status < 0)
5579 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5580 if (status < 0)
5582 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5583 if (status < 0)
5585 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5586 if (status < 0)
5588 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5589 if (status < 0)
5591 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5592 if (status < 0)
5594 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5595 if (status < 0)
5597 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5598 if (status < 0)
5600 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5601 if (status < 0)
5605 status = write16(state, QAM_SY_SP_INV__A,
5607 if (status < 0)
5611 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5612 if (status < 0)
5618 status = set_qam16(state);
5621 status = set_qam32(state);
5625 status = set_qam64(state);
5628 status = set_qam128(state);
5631 status = set_qam256(state);
5634 status = -EINVAL;
5637 if (status < 0)
5641 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5642 if (status < 0)
5648 status = mpegts_dto_setup(state, state->m_operation_mode);
5649 if (status < 0)
5653 status = mpegts_start(state);
5654 if (status < 0)
5656 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5657 if (status < 0)
5659 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5660 if (status < 0)
5662 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5663 if (status < 0)
5667 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5670 if (status < 0)
5677 if (status < 0)
5678 pr_err("Error %d on %s\n", status, __func__);
5679 return status;
5685 int status;
5698 status = power_up_qam(state);
5699 if (status < 0)
5702 status = qam_reset_qam(state);
5703 if (status < 0)
5708 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5709 if (status < 0)
5711 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5712 if (status < 0)
5719 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
5724 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
5728 if (status < 0)
5730 status = bl_direct_cmd(state,
5737 status = -EINVAL;
5739 if (status < 0)
5742 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
5743 if (status < 0)
5745 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5746 if (status < 0)
5748 status = write16(state, IQM_CF_MIDTAP__A,
5750 if (status < 0)
5753 status = write16(state, IQM_RC_STRETCH__A, 21);
5754 if (status < 0)
5756 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5757 if (status < 0)
5759 status = write16(state, IQM_AF_CLP_TH__A, 448);
5760 if (status < 0)
5762 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5763 if (status < 0)
5765 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5766 if (status < 0)
5769 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5770 if (status < 0)
5772 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5773 if (status < 0)
5775 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5776 if (status < 0)
5778 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5779 if (status < 0)
5783 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5784 if (status < 0)
5786 status = write16(state, IQM_CF_DATATH__A, 1000);
5787 if (status < 0)
5789 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5790 if (status < 0)
5792 status = write16(state, IQM_CF_DET_LCT__A, 0);
5793 if (status < 0)
5795 status = write16(state, IQM_CF_WND_LEN__A, 1);
5796 if (status < 0)
5798 status = write16(state, IQM_CF_PKDTH__A, 1);
5799 if (status < 0)
5801 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5802 if (status < 0)
5806 status = set_iqm_af(state, true);
5807 if (status < 0)
5809 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5810 if (status < 0)
5814 status = adc_synchronization(state);
5815 if (status < 0)
5819 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5820 if (status < 0)
5824 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5825 if (status < 0)
5831 status = init_agc(state, true);
5832 if (status < 0)
5834 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
5835 if (status < 0)
5839 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
5840 if (status < 0)
5842 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
5843 if (status < 0)
5847 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5849 if (status < 0)
5850 pr_err("Error %d on %s\n", status, __func__);
5851 return status;
5856 int status;
5861 status = write16(state, SCU_RAM_GPIO__A,
5863 if (status < 0)
5867 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5868 if (status < 0)
5874 status = write16(state, SIO_PDR_SMA_TX_CFG__A,
5876 if (status < 0)
5880 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5881 if (status < 0)
5888 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5889 if (status < 0)
5894 status = write16(state, SIO_PDR_SMA_RX_CFG__A,
5896 if (status < 0)
5900 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5901 if (status < 0)
5908 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5909 if (status < 0)
5914 status = write16(state, SIO_PDR_GPIO_CFG__A,
5916 if (status < 0)
5920 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5921 if (status < 0)
5928 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5929 if (status < 0)
5934 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5936 if (status < 0)
5937 pr_err("Error %d on %s\n", status, __func__);
5938 return status;
5943 int status = 0;
5959 status = write_gpio(state);
5961 if (status < 0)
5962 pr_err("Error %d on %s\n", status, __func__);
5963 return status;
5968 int status = 0;
5984 status = write_gpio(state);
5986 if (status < 0)
5987 pr_err("Error %d on %s\n", status, __func__);
5988 return status;
6000 int status;
6005 status = ConfigureI2CBridge(state, true);
6006 if (status < 0)
6010 status = dvbt_enable_ofdm_token_ring(state, false);
6011 if (status < 0)
6014 status = write16(state, SIO_CC_PWD_MODE__A,
6016 if (status < 0)
6018 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6019 if (status < 0)
6022 status = hi_cfg_command(state);
6024 if (status < 0)
6025 pr_err("Error %d on %s\n", status, __func__);
6027 return status;
6032 int status = 0, n = 0;
6039 status = power_up_device(state);
6040 if (status < 0)
6042 status = drxx_open(state);
6043 if (status < 0)
6046 status = write16(state, SIO_CC_SOFT_RST__A,
6050 if (status < 0)
6052 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6053 if (status < 0)
6061 status = get_device_capabilities(state);
6062 if (status < 0)
6082 status = init_hi(state);
6083 if (status < 0)
6091 status = write16(state, SCU_RAM_GPIO__A,
6093 if (status < 0)
6098 status = mpegts_disable(state);
6099 if (status < 0)
6103 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6104 if (status < 0)
6106 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6107 if (status < 0)
6111 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6113 if (status < 0)
6117 status = write16(state, SIO_BL_COMM_EXEC__A,
6119 if (status < 0)
6121 status = bl_chain_cmd(state, 0, 6, 100);
6122 if (status < 0)
6126 status = download_microcode(state, state->fw->data,
6128 if (status < 0)
6133 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6135 if (status < 0)
6139 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6140 if (status < 0)
6142 status = drxx_open(state);
6143 if (status < 0)
6149 status = ctrl_power_mode(state, &power_mode);
6150 if (status < 0)
6164 status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
6166 if (status < 0)
6173 status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
6175 if (status < 0)
6193 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6194 if (status < 0)
6199 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6200 if (status < 0)
6203 status = mpegts_dto_init(state);
6204 if (status < 0)
6206 status = mpegts_stop(state);
6207 if (status < 0)
6209 status = mpegts_configure_polarity(state);
6210 if (status < 0)
6212 status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
6213 if (status < 0)
6216 status = write_gpio(state);
6217 if (status < 0)
6223 status = power_down_device(state);
6224 if (status < 0)
6246 if (status < 0) {
6249 pr_err("Error %d on %s\n", status, __func__);
6252 return status;
6395 int status;
6421 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6422 if (status < 0)
6423 return status;
6426 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
6427 if (status < 0)
6428 return status;
6454 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6456 if (status < 0)
6457 return status;
6459 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6461 if (status < 0)
6462 return status;
6498 int status;
6515 /* get status */
6561 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16);
6562 if (status < 0)
6566 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16);
6567 if (status < 0)
6572 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16);
6573 if (status < 0)
6577 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16);
6578 if (status < 0)
6582 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16);
6583 if (status < 0)
6587 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16);
6588 if (status < 0)
6614 return status;
6618 static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status)
6629 *status = state->fe_status;
6754 int status;
6811 status = request_firmware(&fw, state->microcode_name,
6813 if (status < 0)