Lines Matching refs:state
25 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
26 static int power_down_qam(struct drxk_state *state);
27 static int set_dvbt_standard(struct drxk_state *state,
29 static int set_qam_standard(struct drxk_state *state,
31 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
33 static int set_dvbt_standard(struct drxk_state *state,
35 static int dvbt_start(struct drxk_state *state);
36 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
38 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
39 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
40 static int switch_antenna_to_qam(struct drxk_state *state);
41 static int switch_antenna_to_dvbt(struct drxk_state *state);
43 static bool is_dvbt(struct drxk_state *state)
45 return state->m_operation_mode == OM_DVBT;
48 static bool is_qam(struct drxk_state *state)
50 return state->m_operation_mode == OM_QAM_ITU_A ||
51 state->m_operation_mode == OM_QAM_ITU_B ||
52 state->m_operation_mode == OM_QAM_ITU_C;
94 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
97 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
100 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
191 static int drxk_i2c_lock(struct drxk_state *state)
193 i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT);
194 state->drxk_i2c_exclusive_lock = true;
199 static void drxk_i2c_unlock(struct drxk_state *state)
201 if (!state->drxk_i2c_exclusive_lock)
204 i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
205 state->drxk_i2c_exclusive_lock = false;
208 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
211 if (state->drxk_i2c_exclusive_lock)
212 return __i2c_transfer(state->i2c, msgs, len);
214 return i2c_transfer(state->i2c, msgs, len);
217 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
223 return drxk_i2c_transfer(state, msgs, 1);
226 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
239 status = drxk_i2c_transfer(state, &msg, 1);
249 static int i2c_read(struct drxk_state *state,
260 status = drxk_i2c_transfer(state, msgs, 2);
283 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
286 u8 adr = state->demod_address, mm1[4], mm2[2], len;
288 if (state->single_master)
303 status = i2c_read(state, adr, mm1, len, mm2, 2);
312 static int read16(struct drxk_state *state, u32 reg, u16 *data)
314 return read16_flags(state, reg, data, 0);
317 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
320 u8 adr = state->demod_address, mm1[4], mm2[4], len;
322 if (state->single_master)
337 status = i2c_read(state, adr, mm1, len, mm2, 4);
347 static int read32(struct drxk_state *state, u32 reg, u32 *data)
349 return read32_flags(state, reg, data, 0);
352 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
354 u8 adr = state->demod_address, mm[6], len;
356 if (state->single_master)
373 return i2c_write(state, adr, mm, len + 2);
376 static int write16(struct drxk_state *state, u32 reg, u16 data)
378 return write16_flags(state, reg, data, 0);
381 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
383 u8 adr = state->demod_address, mm[8], len;
385 if (state->single_master)
404 return i2c_write(state, adr, mm, len + 4);
407 static int write32(struct drxk_state *state, u32 reg, u32 data)
409 return write32_flags(state, reg, data, 0);
412 static int write_block(struct drxk_state *state, u32 address,
418 if (state->single_master)
422 int chunk = blk_size > state->m_chunk_size ?
423 state->m_chunk_size : blk_size;
424 u8 *adr_buf = &state->chunk[0];
434 if (chunk == state->m_chunk_size)
442 memcpy(&state->chunk[adr_length], p_block, chunk);
451 status = i2c_write(state, state->demod_address,
452 &state->chunk[0], chunk + adr_length);
469 static int power_up_device(struct drxk_state *state)
477 status = i2c_read1(state, state->demod_address, &data);
481 status = i2c_write(state, state->demod_address,
487 status = i2c_read1(state, state->demod_address,
496 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
499 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
503 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
507 state->m_current_power_mode = DRX_POWER_UP;
517 static int init_state(struct drxk_state *state)
573 state->m_has_lna = false;
574 state->m_has_dvbt = false;
575 state->m_has_dvbc = false;
576 state->m_has_atv = false;
577 state->m_has_oob = false;
578 state->m_has_audio = false;
580 if (!state->m_chunk_size)
581 state->m_chunk_size = 124;
583 state->m_osc_clock_freq = 0;
584 state->m_smart_ant_inverted = false;
585 state->m_b_p_down_open_bridge = false;
588 state->m_sys_clock_freq = 151875;
591 state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *
594 if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
595 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
596 state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
598 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
600 state->m_b_power_down = (ul_power_down != 0);
602 state->m_drxk_a3_patch_code = false;
606 state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode;
607 state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level;
608 state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level;
609 state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level;
610 state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed;
611 state->m_vsb_pga_cfg = 140;
614 state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode;
615 state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level;
616 state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level;
617 state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level;
618 state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed;
619 state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top;
620 state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current;
621 state->m_vsb_pre_saw_cfg.reference = 0x07;
622 state->m_vsb_pre_saw_cfg.use_pre_saw = true;
624 state->m_Quality83percent = DEFAULT_MER_83;
625 state->m_Quality93percent = DEFAULT_MER_93;
627 state->m_Quality83percent = ulQual83;
628 state->m_Quality93percent = ulQual93;
632 state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode;
633 state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level;
634 state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level;
635 state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level;
636 state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed;
639 state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode;
640 state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level;
641 state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level;
642 state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level;
643 state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed;
644 state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top;
645 state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current;
646 state->m_atv_pre_saw_cfg.reference = 0x04;
647 state->m_atv_pre_saw_cfg.use_pre_saw = true;
651 state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
652 state->m_dvbt_rf_agc_cfg.output_level = 0;
653 state->m_dvbt_rf_agc_cfg.min_output_level = 0;
654 state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;
655 state->m_dvbt_rf_agc_cfg.top = 0x2100;
656 state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;
657 state->m_dvbt_rf_agc_cfg.speed = 1;
661 state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
662 state->m_dvbt_if_agc_cfg.output_level = 0;
663 state->m_dvbt_if_agc_cfg.min_output_level = 0;
664 state->m_dvbt_if_agc_cfg.max_output_level = 9000;
665 state->m_dvbt_if_agc_cfg.top = 13424;
666 state->m_dvbt_if_agc_cfg.cut_off_current = 0;
667 state->m_dvbt_if_agc_cfg.speed = 3;
668 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;
669 state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;
670 /* state->m_dvbtPgaCfg = 140; */
672 state->m_dvbt_pre_saw_cfg.reference = 4;
673 state->m_dvbt_pre_saw_cfg.use_pre_saw = false;
676 state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
677 state->m_qam_rf_agc_cfg.output_level = 0;
678 state->m_qam_rf_agc_cfg.min_output_level = 6023;
679 state->m_qam_rf_agc_cfg.max_output_level = 27000;
680 state->m_qam_rf_agc_cfg.top = 0x2380;
681 state->m_qam_rf_agc_cfg.cut_off_current = 4000;
682 state->m_qam_rf_agc_cfg.speed = 3;
685 state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
686 state->m_qam_if_agc_cfg.output_level = 0;
687 state->m_qam_if_agc_cfg.min_output_level = 0;
688 state->m_qam_if_agc_cfg.max_output_level = 9000;
689 state->m_qam_if_agc_cfg.top = 0x0511;
690 state->m_qam_if_agc_cfg.cut_off_current = 0;
691 state->m_qam_if_agc_cfg.speed = 3;
692 state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;
693 state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;
695 state->m_qam_pga_cfg = 140;
696 state->m_qam_pre_saw_cfg.reference = 4;
697 state->m_qam_pre_saw_cfg.use_pre_saw = false;
699 state->m_operation_mode = OM_NONE;
700 state->m_drxk_state = DRXK_UNINITIALIZED;
703 state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG output */
704 state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */
705 state->m_invert_data = false; /* If TRUE; invert DATA signals */
706 state->m_invert_err = false; /* If TRUE; invert ERR signal */
707 state->m_invert_str = false; /* If TRUE; invert STR signals */
708 state->m_invert_val = false; /* If TRUE; invert VAL signals */
709 state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */
714 state->m_dvbt_bitrate = ul_dvbt_bitrate;
715 state->m_dvbc_bitrate = ul_dvbc_bitrate;
717 state->m_ts_data_strength = (ul_ts_data_strength & 0x07);
720 state->m_mpeg_ts_static_bitrate = 19392658;
721 state->m_disable_te_ihandling = false;
724 state->m_insert_rs_byte = true;
726 state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
728 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;
729 state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
731 state->m_demod_lock_time_out = ul_demod_lock_time_out;
734 state->m_constellation = DRX_CONSTELLATION_AUTO;
735 state->m_qam_interleave_mode = DRXK_QAM_I12_J17;
736 state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */
737 state->m_fec_rs_prescale = 1;
739 state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;
740 state->m_agcfast_clip_ctrl_delay = 0;
742 state->m_gpio_cfg = ul_gpio_cfg;
744 state->m_b_power_down = false;
745 state->m_current_power_mode = DRX_POWER_DOWN;
747 state->m_rfmirror = (ul_rf_mirror == 0);
748 state->m_if_agc_pol = false;
752 static int drxx_open(struct drxk_state *state)
761 status = write16(state, SCU_RAM_GPIO__A,
766 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
769 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
772 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
775 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
778 status = write16(state, SIO_TOP_COMM_KEY__A, key);
785 static int get_device_capabilities(struct drxk_state *state)
796 status = write16(state, SCU_RAM_GPIO__A,
800 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
803 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
806 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
816 state->m_osc_clock_freq = 27000;
820 state->m_osc_clock_freq = 20250;
824 state->m_osc_clock_freq = 20250;
834 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
843 state->m_device_spin = DRXK_SPIN_A1;
847 state->m_device_spin = DRXK_SPIN_A2;
851 state->m_device_spin = DRXK_SPIN_A3;
855 state->m_device_spin = DRXK_SPIN_UNKNOWN;
863 state->m_has_lna = false;
864 state->m_has_oob = false;
865 state->m_has_atv = false;
866 state->m_has_audio = false;
867 state->m_has_dvbt = true;
868 state->m_has_dvbc = true;
869 state->m_has_sawsw = true;
870 state->m_has_gpio2 = false;
871 state->m_has_gpio1 = false;
872 state->m_has_irqn = false;
876 state->m_has_lna = false;
877 state->m_has_oob = false;
878 state->m_has_atv = true;
879 state->m_has_audio = false;
880 state->m_has_dvbt = true;
881 state->m_has_dvbc = false;
882 state->m_has_sawsw = true;
883 state->m_has_gpio2 = true;
884 state->m_has_gpio1 = true;
885 state->m_has_irqn = false;
889 state->m_has_lna = false;
890 state->m_has_oob = false;
891 state->m_has_atv = true;
892 state->m_has_audio = false;
893 state->m_has_dvbt = true;
894 state->m_has_dvbc = false;
895 state->m_has_sawsw = true;
896 state->m_has_gpio2 = true;
897 state->m_has_gpio1 = true;
898 state->m_has_irqn = false;
902 state->m_has_lna = false;
903 state->m_has_oob = false;
904 state->m_has_atv = true;
905 state->m_has_audio = true;
906 state->m_has_dvbt = true;
907 state->m_has_dvbc = false;
908 state->m_has_sawsw = true;
909 state->m_has_gpio2 = true;
910 state->m_has_gpio1 = true;
911 state->m_has_irqn = false;
915 state->m_has_lna = false;
916 state->m_has_oob = false;
917 state->m_has_atv = true;
918 state->m_has_audio = true;
919 state->m_has_dvbt = true;
920 state->m_has_dvbc = true;
921 state->m_has_sawsw = true;
922 state->m_has_gpio2 = true;
923 state->m_has_gpio1 = true;
924 state->m_has_irqn = false;
928 state->m_has_lna = false;
929 state->m_has_oob = false;
930 state->m_has_atv = true;
931 state->m_has_audio = true;
932 state->m_has_dvbt = true;
933 state->m_has_dvbc = true;
934 state->m_has_sawsw = true;
935 state->m_has_gpio2 = true;
936 state->m_has_gpio1 = true;
937 state->m_has_irqn = false;
941 state->m_has_lna = false;
942 state->m_has_oob = false;
943 state->m_has_atv = true;
944 state->m_has_audio = true;
945 state->m_has_dvbt = true;
946 state->m_has_dvbc = true;
947 state->m_has_sawsw = true;
948 state->m_has_gpio2 = true;
949 state->m_has_gpio1 = true;
950 state->m_has_irqn = false;
954 state->m_has_lna = false;
955 state->m_has_oob = false;
956 state->m_has_atv = true;
957 state->m_has_audio = false;
958 state->m_has_dvbt = true;
959 state->m_has_dvbc = true;
960 state->m_has_sawsw = true;
961 state->m_has_gpio2 = true;
962 state->m_has_gpio1 = true;
963 state->m_has_irqn = false;
974 state->m_osc_clock_freq / 1000,
975 state->m_osc_clock_freq % 1000);
985 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)
993 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1001 ((state->m_hi_cfg_ctrl) &
1012 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1017 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
1026 static int hi_cfg_command(struct drxk_state *state)
1032 mutex_lock(&state->mutex);
1034 status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
1035 state->m_hi_cfg_timeout);
1038 status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
1039 state->m_hi_cfg_ctrl);
1042 status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
1043 state->m_hi_cfg_wake_up_key);
1046 status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
1047 state->m_hi_cfg_bridge_delay);
1050 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
1051 state->m_hi_cfg_timing_div);
1054 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
1058 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);
1062 state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1064 mutex_unlock(&state->mutex);
1070 static int init_hi(struct drxk_state *state)
1074 state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
1075 state->m_hi_cfg_timeout = 0x96FF;
1077 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1079 return hi_cfg_command(state);
1082 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
1091 state->m_enable_parallel ? "parallel" : "serial");
1094 status = write16(state, SCU_RAM_GPIO__A,
1100 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1106 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1109 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1112 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1115 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1118 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1121 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1124 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1127 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1130 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1133 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1136 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1139 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1145 ((state->m_ts_data_strength <<
1147 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<
1151 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
1155 if (state->enable_merr_cfg)
1158 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1161 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1165 if (state->m_enable_parallel) {
1167 status = write16(state, SIO_PDR_MD1_CFG__A,
1171 status = write16(state, SIO_PDR_MD2_CFG__A,
1175 status = write16(state, SIO_PDR_MD3_CFG__A,
1179 status = write16(state, SIO_PDR_MD4_CFG__A,
1183 status = write16(state, SIO_PDR_MD5_CFG__A,
1187 status = write16(state, SIO_PDR_MD6_CFG__A,
1191 status = write16(state, SIO_PDR_MD7_CFG__A,
1196 sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<
1200 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1203 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1206 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1209 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1212 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1215 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1218 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1222 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
1225 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
1230 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1234 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1241 static int mpegts_disable(struct drxk_state *state)
1245 return mpegts_configure_pins(state, false);
1248 static int bl_chain_cmd(struct drxk_state *state,
1256 mutex_lock(&state->mutex);
1257 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1260 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
1263 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
1266 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1273 status = read16(state, SIO_BL_STATUS__A, &bl_status);
1288 mutex_unlock(&state->mutex);
1293 static int download_microcode(struct drxk_state *state,
1346 status = write_block(state, address, block_size, p_src);
1357 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
1372 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1378 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
1382 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1395 static int mpegts_stop(struct drxk_state *state)
1404 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1408 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1413 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
1417 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
1426 static int scu_command(struct drxk_state *state,
1449 mutex_lock(&state->mutex);
1462 write_block(state, SCU_RAM_PARAM_0__A -
1468 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
1483 status = read16(state, SCU_RAM_PARAM_0__A - ii,
1522 mutex_unlock(&state->mutex);
1526 static int set_iqm_af(struct drxk_state *state, bool active)
1534 status = read16(state, IQM_AF_STDBY__A, &data);
1552 status = write16(state, IQM_AF_STDBY__A, data);
1560 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)
1593 if (state->m_current_power_mode == *mode)
1597 if (state->m_current_power_mode != DRX_POWER_UP) {
1598 status = power_up_device(state);
1601 status = dvbt_enable_ofdm_token_ring(state, true);
1618 switch (state->m_operation_mode) {
1620 status = mpegts_stop(state);
1623 status = power_down_dvbt(state, false);
1629 status = mpegts_stop(state);
1632 status = power_down_qam(state);
1639 status = dvbt_enable_ofdm_token_ring(state, false);
1642 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
1645 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1650 state->m_hi_cfg_ctrl |=
1652 status = hi_cfg_command(state);
1657 state->m_current_power_mode = *mode;
1666 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)
1675 status = read16(state, SCU_COMM_EXEC__A, &data);
1680 status = scu_command(state,
1687 status = scu_command(state,
1696 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1699 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1702 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1707 status = set_iqm_af(state, false);
1713 status = ctrl_power_mode(state, &power_mode);
1723 static int setoperation_mode(struct drxk_state *state,
1736 status = write16(state, SCU_RAM_GPIO__A,
1742 if (state->m_operation_mode == o_mode)
1745 switch (state->m_operation_mode) {
1750 status = mpegts_stop(state);
1753 status = power_down_dvbt(state, true);
1756 state->m_operation_mode = OM_NONE;
1760 status = mpegts_stop(state);
1763 status = power_down_qam(state);
1766 state->m_operation_mode = OM_NONE;
1780 state->m_operation_mode = o_mode;
1781 status = set_dvbt_standard(state, o_mode);
1788 (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');
1789 state->m_operation_mode = o_mode;
1790 status = set_qam_standard(state, o_mode);
1804 static int start(struct drxk_state *state, s32 offset_freq,
1813 if (state->m_drxk_state != DRXK_STOPPED &&
1814 state->m_drxk_state != DRXK_DTV_STARTED)
1817 state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);
1820 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;
1824 switch (state->m_operation_mode) {
1828 status = set_qam(state, i_freqk_hz, offsetk_hz);
1831 state->m_drxk_state = DRXK_DTV_STARTED;
1835 status = mpegts_stop(state);
1838 status = set_dvbt(state, i_freqk_hz, offsetk_hz);
1841 status = dvbt_start(state);
1844 state->m_drxk_state = DRXK_DTV_STARTED;
1855 static int shut_down(struct drxk_state *state)
1859 mpegts_stop(state);
1863 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)
1875 switch (state->m_operation_mode) {
1879 status = get_qam_lock_status(state, p_lock_status);
1882 status = get_dvbt_lock_status(state, p_lock_status);
1886 state->m_operation_mode, __func__);
1895 static int mpegts_start(struct drxk_state *state)
1902 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1906 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1909 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1916 static int mpegts_dto_init(struct drxk_state *state)
1923 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1926 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1929 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1932 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1935 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1938 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1941 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1944 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1949 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1952 status = write16(state, FEC_OC_SNC_LWM__A, 2);
1955 status = write16(state, FEC_OC_SNC_HWM__A, 12);
1963 static int mpegts_dto_setup(struct drxk_state *state,
1983 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
1986 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
1991 if (state->m_insert_rs_byte) {
2002 if (!state->m_enable_parallel) {
2009 max_bit_rate = state->m_dvbt_bitrate;
2012 static_clk = state->m_dvbt_static_clk;
2018 max_bit_rate = state->m_dvbc_bitrate;
2019 static_clk = state->m_dvbc_static_clk;
2051 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)
2066 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
2069 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
2072 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
2075 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
2078 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
2081 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
2086 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
2089 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
2093 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
2100 static int mpegts_configure_polarity(struct drxk_state *state)
2115 if (state->m_invert_data)
2118 if (state->m_invert_err)
2121 if (state->m_invert_str)
2124 if (state->m_invert_val)
2127 if (state->m_invert_clk)
2130 return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);
2135 static int set_agc_rf(struct drxk_state *state,
2150 status = read16(state, IQM_AF_STDBY__A, &data);
2154 status = write16(state, IQM_AF_STDBY__A, data);
2157 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2165 if (state->m_rf_agc_pol)
2169 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2174 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2183 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2187 if (is_dvbt(state))
2188 p_if_agc_settings = &state->m_dvbt_if_agc_cfg;
2189 else if (is_qam(state))
2190 p_if_agc_settings = &state->m_qam_if_agc_cfg;
2192 p_if_agc_settings = &state->m_atv_if_agc_cfg;
2200 status = write16(state,
2208 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
2214 status = write16(state, SCU_RAM_AGC_RF_MAX__A,
2223 status = read16(state, IQM_AF_STDBY__A, &data);
2227 status = write16(state, IQM_AF_STDBY__A, data);
2232 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2236 if (state->m_rf_agc_pol)
2240 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2245 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2250 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
2258 status = read16(state, IQM_AF_STDBY__A, &data);
2262 status = write16(state, IQM_AF_STDBY__A, data);
2267 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2271 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2288 static int set_agc_if(struct drxk_state *state,
2301 status = read16(state, IQM_AF_STDBY__A, &data);
2305 status = write16(state, IQM_AF_STDBY__A, data);
2309 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2317 if (state->m_if_agc_pol)
2321 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2326 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2334 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2338 if (is_qam(state))
2339 p_rf_agc_settings = &state->m_qam_rf_agc_cfg;
2341 p_rf_agc_settings = &state->m_atv_rf_agc_cfg;
2345 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2354 status = read16(state, IQM_AF_STDBY__A, &data);
2358 status = write16(state, IQM_AF_STDBY__A, data);
2362 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2370 if (state->m_if_agc_pol)
2374 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2379 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2388 status = read16(state, IQM_AF_STDBY__A, &data);
2392 status = write16(state, IQM_AF_STDBY__A, data);
2397 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2401 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2409 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
2416 static int get_qam_signal_to_noise(struct drxk_state *state,
2431 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
2437 switch (state->props.modulation) {
2465 static int get_dvbt_signal_to_noise(struct drxk_state *state,
2485 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
2489 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
2493 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
2497 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
2507 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data);
2516 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
2569 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)
2574 switch (state->m_operation_mode) {
2576 return get_dvbt_signal_to_noise(state, p_signal_to_noise);
2579 return get_qam_signal_to_noise(state, p_signal_to_noise);
2587 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2621 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2624 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2630 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2654 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2666 status = get_qam_signal_to_noise(state, &signal_to_noise);
2670 switch (state->props.modulation) {
2701 static int get_quality(struct drxk_state *state, s32 *p_quality)
2705 switch (state->m_operation_mode) {
2707 return get_dvbt_quality(state, p_quality);
2709 return get_dvbc_quality(state, p_quality);
2731 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)
2737 if (state->m_drxk_state == DRXK_UNINITIALIZED)
2739 if (state->m_drxk_state == DRXK_POWERED_DOWN)
2742 if (state->no_i2c_bridge)
2745 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
2750 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2755 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2761 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);
2769 static int set_pre_saw(struct drxk_state *state,
2780 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
2787 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,
2798 mutex_lock(&state->mutex);
2799 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2802 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2805 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2808 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
2811 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
2814 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2820 status = read16(state, SIO_BL_STATUS__A, &bl_status);
2833 mutex_unlock(&state->mutex);
2838 static int adc_sync_measurement(struct drxk_state *state, u16 *count)
2846 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2849 status = write16(state, IQM_AF_START_LOCK__A, 1);
2854 status = read16(state, IQM_AF_PHASE0__A, &data);
2859 status = read16(state, IQM_AF_PHASE1__A, &data);
2864 status = read16(state, IQM_AF_PHASE2__A, &data);
2876 static int adc_synchronization(struct drxk_state *state)
2883 status = adc_sync_measurement(state, &count);
2891 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
2904 status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
2907 status = adc_sync_measurement(state, &count);
2920 static int set_frequency_shifter(struct drxk_state *state,
2927 bool tuner_mirror = !state->m_b_mirror_freq_spect;
2932 u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);
2943 if ((state->m_operation_mode == OM_QAM_ITU_A) ||
2944 (state->m_operation_mode == OM_QAM_ITU_C) ||
2945 (state->m_operation_mode == OM_DVBT))
2969 image_to_select = state->m_rfmirror ^ tuner_mirror ^
2971 state->m_iqm_fs_rate_ofs =
2975 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;
2979 status = write32(state, IQM_FS_RATE_OFS_LO__A,
2980 state->m_iqm_fs_rate_ofs);
2986 static int init_agc(struct drxk_state *state, bool is_dtv)
3016 if (!is_qam(state)) {
3018 __func__, state->m_operation_mode);
3036 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
3038 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3043 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
3046 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
3049 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
3052 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
3055 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
3059 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
3063 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3066 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3069 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3072 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3075 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
3078 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
3082 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
3086 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
3090 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
3094 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3097 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3100 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3104 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3107 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
3110 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
3113 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
3116 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
3119 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3122 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3125 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3128 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3131 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3134 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3137 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3140 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3143 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3146 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3149 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3152 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3155 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3158 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3163 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3173 status = write16(state, SCU_RAM_AGC_KI__A, data);
3180 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)
3186 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3188 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
3195 static int dvbt_sc_command(struct drxk_state *state,
3207 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
3219 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3231 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3250 status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3254 status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3259 status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3272 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3279 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
3296 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3316 static int power_up_dvbt(struct drxk_state *state)
3322 status = ctrl_power_mode(state, &power_mode);
3328 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)
3334 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3336 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3343 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
3351 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3355 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3363 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
3370 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3391 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3398 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,
3413 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3431 static int dvbt_activate_presets(struct drxk_state *state)
3441 status = dvbt_ctrl_set_inc_enable(state, &setincenable);
3444 status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
3447 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
3450 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
3453 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
3454 state->m_dvbt_if_agc_cfg.ingain_tgt_max);
3471 static int set_dvbt_standard(struct drxk_state *state,
3480 power_up_dvbt(state);
3482 switch_antenna_to_dvbt(state);
3484 status = scu_command(state,
3492 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3499 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3502 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3505 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3511 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3515 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3519 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3523 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3526 status = set_iqm_af(state, true);
3530 status = write16(state, IQM_AF_AGC_RF__A, 0);
3535 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3538 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3541 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3545 status = write16(state, IQM_RC_STRETCH__A, 16);
3548 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3551 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3554 status = write16(state, IQM_CF_SCALE__A, 1600);
3557 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3562 status = write16(state, IQM_AF_CLP_TH__A, 448);
3565 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3569 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
3574 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3577 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3581 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3584 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3589 status = adc_synchronization(state);
3592 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
3597 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3601 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
3604 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
3609 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3613 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3618 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3622 if (!state->m_drxk_a3_rom_code) {
3624 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3625 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
3632 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3635 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3641 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3647 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3651 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3655 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3660 status = mpegts_dto_setup(state, OM_DVBT);
3664 status = dvbt_activate_presets(state);
3680 static int dvbt_start(struct drxk_state *state)
3690 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
3696 status = mpegts_start(state);
3699 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3717 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3731 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3738 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3743 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3746 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3752 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3759 switch (state->props.transmission_mode) {
3773 switch (state->props.guard_interval) {
3793 switch (state->props.hierarchy) {
3814 switch (state->props.modulation) {
3851 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3857 switch (state->props.code_rate_HP) {
3892 switch (state->props.bandwidth_hz) {
3894 state->props.bandwidth_hz = 8000000;
3898 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3903 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3907 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3911 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3915 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3922 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3927 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3931 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3935 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3939 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3946 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3951 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3955 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3959 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3963 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3987 ((state->m_sys_clock_freq *
4000 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
4011 status = set_frequency_shifter(state, intermediate_freqk_hz,
4019 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4024 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4027 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4032 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
4044 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4049 if (!state->m_drxk_a3_rom_code)
4050 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
4068 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)
4084 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
4090 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
4109 static int power_up_qam(struct drxk_state *state)
4115 status = ctrl_power_mode(state, &power_mode);
4124 static int power_down_qam(struct drxk_state *state)
4131 status = read16(state, SCU_COMM_EXEC__A, &data);
4140 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4143 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
4150 status = set_iqm_af(state, false);
4172 static int set_qam_measurement(struct drxk_state *state,
4233 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
4236 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
4240 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
4247 static int set_qam16(struct drxk_state *state)
4254 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4257 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4260 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4263 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4266 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4269 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4273 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4276 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4279 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4282 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4285 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4288 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4292 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4295 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4298 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4303 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4309 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4312 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4315 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4318 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4321 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4324 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4327 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4330 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4334 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4337 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4340 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4343 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4346 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4349 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4352 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4355 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4358 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4361 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4364 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4367 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4374 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4377 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4380 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4383 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4386 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4389 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4393 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4396 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4399 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4406 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4409 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4412 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4415 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4418 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4421 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4424 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4441 static int set_qam32(struct drxk_state *state)
4449 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4452 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4455 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4458 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4461 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4464 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4469 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4472 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4475 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4478 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4481 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4484 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4488 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4491 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4494 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4500 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4508 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4511 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4514 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4517 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4520 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4523 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4526 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4529 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4533 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4536 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4539 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4542 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4545 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4548 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4551 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4554 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4557 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4560 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4563 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4566 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4573 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4576 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4579 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4582 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4585 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4588 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4592 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4595 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4598 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4605 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4608 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4611 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4614 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4617 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4620 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4623 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4637 static int set_qam64(struct drxk_state *state)
4644 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4647 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4650 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4653 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4656 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4659 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4664 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4667 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4670 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4673 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4676 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4679 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4683 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4686 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4689 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4694 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4702 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4705 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4708 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4711 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4714 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4717 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4720 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4723 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4727 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4730 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4733 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4736 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4739 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4742 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4745 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4748 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4751 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4754 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4757 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4760 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4767 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4770 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4773 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4776 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4779 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4782 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4786 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4789 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4792 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4799 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4802 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4805 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4808 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4811 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4814 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4817 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4832 static int set_qam128(struct drxk_state *state)
4839 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4842 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4845 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4848 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4851 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4854 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4859 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4862 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4865 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4868 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4871 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4874 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4878 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4881 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4884 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4891 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4899 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4902 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4905 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4908 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4911 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4914 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4917 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4920 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4924 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4927 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4930 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4933 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4936 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4939 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4942 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4945 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4948 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4951 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4954 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4957 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4964 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4967 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4970 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4973 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4976 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4979 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4983 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4986 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
4990 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
4996 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
4999 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5002 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5005 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5008 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5011 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5014 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5029 static int set_qam256(struct drxk_state *state)
5036 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5039 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5042 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5045 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5048 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5051 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5056 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5059 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5062 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5065 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5068 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5071 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5075 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5078 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5081 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5087 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
5095 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5098 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5101 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5104 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5107 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5110 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5113 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5116 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5120 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5123 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5126 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5129 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5132 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5135 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5138 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5141 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5144 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5147 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5150 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5153 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5160 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5163 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5166 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5169 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5172 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5175 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5179 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5182 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5185 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5192 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5195 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5198 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5201 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5204 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5207 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5210 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5225 static int qam_reset_qam(struct drxk_state *state)
5232 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5236 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5253 static int qam_set_symbolrate(struct drxk_state *state)
5264 adc_frequency = (state->m_sys_clock_freq * 1000) / 3;
5266 if (state->props.symbol_rate <= 1188750)
5268 else if (state->props.symbol_rate <= 2377500)
5270 else if (state->props.symbol_rate <= 4755000)
5272 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5279 symb_freq = state->props.symbol_rate * (1 << ratesel);
5288 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
5291 state->m_iqm_rc_rate = iqm_rc_rate;
5295 symb_freq = state->props.symbol_rate;
5306 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
5323 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)
5330 status = scu_command(state,
5364 static int qam_demodulator_command(struct drxk_state *state,
5371 set_param_parameters[0] = state->m_constellation; /* modulation */
5377 if (state->m_operation_mode == OM_QAM_ITU_C)
5382 status = scu_command(state,
5389 status = scu_command(state,
5395 if (state->m_operation_mode == OM_QAM_ITU_C)
5405 status = scu_command(state,
5422 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5427 int qam_demod_param_count = state->qam_demod_parameter_count;
5436 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5439 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5442 status = qam_reset_qam(state);
5451 status = qam_set_symbolrate(state);
5456 switch (state->props.modulation) {
5458 state->m_constellation = DRX_CONSTELLATION_QAM256;
5462 state->m_constellation = DRX_CONSTELLATION_QAM64;
5465 state->m_constellation = DRX_CONSTELLATION_QAM16;
5468 state->m_constellation = DRX_CONSTELLATION_QAM32;
5471 state->m_constellation = DRX_CONSTELLATION_QAM128;
5482 if (state->qam_demod_parameter_count == 4
5483 || !state->qam_demod_parameter_count) {
5485 status = qam_demodulator_command(state, qam_demod_param_count);
5491 if (state->qam_demod_parameter_count == 2
5492 || (!state->qam_demod_parameter_count && status < 0)) {
5494 status = qam_demodulator_command(state, qam_demod_param_count);
5501 state->qam_demod_parameter_count,
5502 state->microcode_name);
5504 } else if (!state->qam_demod_parameter_count) {
5513 state->qam_demod_parameter_count = qam_demod_param_count;
5525 status = set_frequency_shifter(state, intermediate_freqk_hz,
5531 status = set_qam_measurement(state, state->m_constellation,
5532 state->props.symbol_rate);
5537 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5540 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5545 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5548 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5551 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5554 status = write16(state, QAM_LC_MODE__A, 7);
5558 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5561 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5564 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5567 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5570 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5573 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5576 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5579 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5582 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5585 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5588 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5591 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5594 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5597 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5600 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5605 status = write16(state, QAM_SY_SP_INV__A,
5611 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5616 switch (state->props.modulation) {
5618 status = set_qam16(state);
5621 status = set_qam32(state);
5625 status = set_qam64(state);
5628 status = set_qam128(state);
5631 status = set_qam256(state);
5641 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5648 status = mpegts_dto_setup(state, state->m_operation_mode);
5653 status = mpegts_start(state);
5656 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5659 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5662 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5667 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5682 static int set_qam_standard(struct drxk_state *state,
5695 switch_antenna_to_qam(state);
5698 status = power_up_qam(state);
5702 status = qam_reset_qam(state);
5708 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5711 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5719 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
5724 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
5730 status = bl_direct_cmd(state,
5742 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
5745 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5748 status = write16(state, IQM_CF_MIDTAP__A,
5753 status = write16(state, IQM_RC_STRETCH__A, 21);
5756 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5759 status = write16(state, IQM_AF_CLP_TH__A, 448);
5762 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5765 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5769 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5772 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5775 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5778 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5783 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5786 status = write16(state, IQM_CF_DATATH__A, 1000);
5789 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5792 status = write16(state, IQM_CF_DET_LCT__A, 0);
5795 status = write16(state, IQM_CF_WND_LEN__A, 1);
5798 status = write16(state, IQM_CF_PKDTH__A, 1);
5801 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5806 status = set_iqm_af(state, true);
5809 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5814 status = adc_synchronization(state);
5819 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5824 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5831 status = init_agc(state, true);
5834 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
5839 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
5842 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
5847 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5854 static int write_gpio(struct drxk_state *state)
5861 status = write16(state, SCU_RAM_GPIO__A,
5867 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5871 if (state->m_has_sawsw) {
5872 if (state->uio_mask & 0x0001) { /* UIO-1 */
5874 status = write16(state, SIO_PDR_SMA_TX_CFG__A,
5875 state->m_gpio_cfg);
5880 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5883 if ((state->m_gpio & 0x0001) == 0)
5888 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5892 if (state->uio_mask & 0x0002) { /* UIO-2 */
5894 status = write16(state, SIO_PDR_SMA_RX_CFG__A,
5895 state->m_gpio_cfg);
5900 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5903 if ((state->m_gpio & 0x0002) == 0)
5908 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5912 if (state->uio_mask & 0x0004) { /* UIO-3 */
5914 status = write16(state, SIO_PDR_GPIO_CFG__A,
5915 state->m_gpio_cfg);
5920 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5923 if ((state->m_gpio & 0x0004) == 0)
5928 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5934 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5941 static int switch_antenna_to_qam(struct drxk_state *state)
5948 if (!state->antenna_gpio)
5951 gpio_state = state->m_gpio & state->antenna_gpio;
5953 if (state->antenna_dvbt ^ gpio_state) {
5955 if (state->antenna_dvbt)
5956 state->m_gpio &= ~state->antenna_gpio;
5958 state->m_gpio |= state->antenna_gpio;
5959 status = write_gpio(state);
5966 static int switch_antenna_to_dvbt(struct drxk_state *state)
5973 if (!state->antenna_gpio)
5976 gpio_state = state->m_gpio & state->antenna_gpio;
5978 if (!(state->antenna_dvbt ^ gpio_state)) {
5980 if (state->antenna_dvbt)
5981 state->m_gpio |= state->antenna_gpio;
5983 state->m_gpio &= ~state->antenna_gpio;
5984 status = write_gpio(state);
5992 static int power_down_device(struct drxk_state *state)
6003 if (state->m_b_p_down_open_bridge) {
6005 status = ConfigureI2CBridge(state, true);
6010 status = dvbt_enable_ofdm_token_ring(state, false);
6014 status = write16(state, SIO_CC_PWD_MODE__A,
6018 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6021 state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
6022 status = hi_cfg_command(state);
6030 static int init_drxk(struct drxk_state *state)
6037 if (state->m_drxk_state == DRXK_UNINITIALIZED) {
6038 drxk_i2c_lock(state);
6039 status = power_up_device(state);
6042 status = drxx_open(state);
6046 status = write16(state, SIO_CC_SOFT_RST__A,
6052 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6060 state->m_drxk_a3_patch_code = true;
6061 status = get_device_capabilities(state);
6068 state->m_hi_cfg_bridge_delay =
6069 (u16) ((state->m_osc_clock_freq / 1000) *
6072 if (state->m_hi_cfg_bridge_delay >
6074 state->m_hi_cfg_bridge_delay =
6078 state->m_hi_cfg_bridge_delay +=
6079 state->m_hi_cfg_bridge_delay <<
6082 status = init_hi(state);
6087 if (!(state->m_DRXK_A1_ROM_CODE)
6088 && !(state->m_DRXK_A2_ROM_CODE))
6091 status = write16(state, SCU_RAM_GPIO__A,
6098 status = mpegts_disable(state);
6103 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6106 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6111 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6117 status = write16(state, SIO_BL_COMM_EXEC__A,
6121 status = bl_chain_cmd(state, 0, 6, 100);
6125 if (state->fw) {
6126 status = download_microcode(state, state->fw->data,
6127 state->fw->size);
6133 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6139 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6142 status = drxx_open(state);
6149 status = ctrl_power_mode(state, &power_mode);
6164 status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
6173 status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
6193 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6199 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6203 status = mpegts_dto_init(state);
6206 status = mpegts_stop(state);
6209 status = mpegts_configure_polarity(state);
6212 status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
6216 status = write_gpio(state);
6220 state->m_drxk_state = DRXK_STOPPED;
6222 if (state->m_b_power_down) {
6223 status = power_down_device(state);
6226 state->m_drxk_state = DRXK_POWERED_DOWN;
6228 state->m_drxk_state = DRXK_STOPPED;
6232 if (state->m_has_dvbc) {
6233 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6234 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6235 strlcat(state->frontend.ops.info.name, " DVB-C",
6236 sizeof(state->frontend.ops.info.name));
6238 if (state->m_has_dvbt) {
6239 state->frontend.ops.delsys[n++] = SYS_DVBT;
6240 strlcat(state->frontend.ops.info.name, " DVB-T",
6241 sizeof(state->frontend.ops.info.name));
6243 drxk_i2c_unlock(state);
6247 state->m_drxk_state = DRXK_NO_DEV;
6248 drxk_i2c_unlock(state);
6258 struct drxk_state *state = context;
6263 state->microcode_name);
6265 state->microcode_name);
6266 state->microcode_name = NULL;
6279 state->fw = fw;
6281 init_drxk(state);
6286 struct drxk_state *state = fe->demodulator_priv;
6289 release_firmware(state->fw);
6291 kfree(state);
6296 struct drxk_state *state = fe->demodulator_priv;
6300 if (state->m_drxk_state == DRXK_NO_DEV)
6302 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6305 shut_down(state);
6311 struct drxk_state *state = fe->demodulator_priv;
6315 if (state->m_drxk_state == DRXK_NO_DEV)
6318 return ConfigureI2CBridge(state, enable ? true : false);
6325 struct drxk_state *state = fe->demodulator_priv;
6330 if (state->m_drxk_state == DRXK_NO_DEV)
6333 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6348 old_delsys = state->props.delivery_system;
6349 state->props = *p;
6352 shut_down(state);
6356 if (!state->m_has_dvbc)
6358 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?
6360 if (state->m_itut_annex_c)
6361 setoperation_mode(state, OM_QAM_ITU_C);
6363 setoperation_mode(state, OM_QAM_ITU_A);
6366 if (!state->m_has_dvbt)
6368 setoperation_mode(state, OM_DVBT);
6376 start(state, 0, IF);
6393 static int get_strength(struct drxk_state *state, u64 *strength)
6408 if (is_dvbt(state)) {
6409 rf_agc = state->m_dvbt_rf_agc_cfg;
6410 if_agc = state->m_dvbt_if_agc_cfg;
6411 } else if (is_qam(state)) {
6412 rf_agc = state->m_qam_rf_agc_cfg;
6413 if_agc = state->m_qam_if_agc_cfg;
6415 rf_agc = state->m_atv_rf_agc_cfg;
6416 if_agc = state->m_atv_if_agc_cfg;
6421 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6426 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
6454 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6459 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6497 struct drxk_state *state = fe->demodulator_priv;
6510 if (state->m_drxk_state == DRXK_NO_DEV)
6512 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6516 state->fe_status = 0;
6517 get_lock_status(state, &stat);
6519 state->fe_status |= 0x1f;
6521 state->fe_status |= 0x0f;
6523 state->fe_status |= 0x07;
6528 get_strength(state, &c->strength.stat[0].uvalue);
6533 get_signal_to_noise(state, &cnr);
6561 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16);
6566 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16);
6572 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16);
6577 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16);
6582 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16);
6587 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16);
6591 write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
6620 struct drxk_state *state = fe->demodulator_priv;
6629 *status = state->fe_status;
6637 struct drxk_state *state = fe->demodulator_priv;
6642 if (state->m_drxk_state == DRXK_NO_DEV)
6644 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6653 struct drxk_state *state = fe->demodulator_priv;
6658 if (state->m_drxk_state == DRXK_NO_DEV)
6660 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6663 get_signal_to_noise(state, &snr2);
6674 struct drxk_state *state = fe->demodulator_priv;
6679 if (state->m_drxk_state == DRXK_NO_DEV)
6681 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6684 dvbtqam_get_acc_pkt_err(state, &err);
6692 struct drxk_state *state = fe->demodulator_priv;
6697 if (state->m_drxk_state == DRXK_NO_DEV)
6699 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6752 struct drxk_state *state = NULL;
6757 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6758 if (!state)
6761 state->i2c = i2c;
6762 state->demod_address = adr;
6763 state->single_master = config->single_master;
6764 state->microcode_name = config->microcode_name;
6765 state->qam_demod_parameter_count = config->qam_demod_parameter_count;
6766 state->no_i2c_bridge = config->no_i2c_bridge;
6767 state->antenna_gpio = config->antenna_gpio;
6768 state->antenna_dvbt = config->antenna_dvbt;
6769 state->m_chunk_size = config->chunk_size;
6770 state->enable_merr_cfg = config->enable_merr_cfg;
6773 state->m_dvbt_static_clk = false;
6774 state->m_dvbc_static_clk = false;
6776 state->m_dvbt_static_clk = true;
6777 state->m_dvbc_static_clk = true;
6782 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;
6784 state->m_ts_clockk_strength = 0x06;
6787 state->m_enable_parallel = true;
6789 state->m_enable_parallel = false;
6792 state->uio_mask = config->antenna_gpio;
6795 if (!state->antenna_dvbt && state->antenna_gpio)
6796 state->m_gpio |= state->antenna_gpio;
6798 state->m_gpio &= ~state->antenna_gpio;
6800 mutex_init(&state->mutex);
6802 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6803 state->frontend.demodulator_priv = state;
6805 init_state(state);
6808 if (state->microcode_name) {
6811 status = request_firmware(&fw, state->microcode_name,
6812 state->i2c->dev.parent);
6815 load_firmware_cb(fw, state);
6816 } else if (init_drxk(state) < 0)
6821 p = &state->frontend.dtv_property_cache;
6841 return &state->frontend;
6845 kfree(state);