Lines Matching refs:status
317 int status = 0;
322 while (!status) {
335 status = WriteBlock(state, Address, Length * 2, pTable, 0);
338 return status;
357 int status;
361 status = WriteTable(state, state->m_InitCE);
362 if (status < 0)
370 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
371 if (status < 0)
374 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
375 if (status < 0)
378 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
379 if (status < 0)
382 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
383 if (status < 0)
388 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
389 if (status < 0)
392 return status;
397 int status = 0;
405 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
406 if (status < 0)
413 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
414 if (status < 0)
416 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
417 if (status < 0)
419 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
420 if (status < 0)
422 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
423 if (status < 0)
427 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
428 if (status < 0)
430 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
431 if (status < 0)
436 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
437 if (status < 0)
442 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
443 if (status < 0)
448 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
449 if (status < 0)
451 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
452 if (status < 0)
454 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
455 if (status < 0)
459 return status;
464 int status = 0;
468 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
469 if (status < 0)
473 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
474 if (status < 0)
476 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
477 if (status < 0)
481 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
482 if (status < 0)
486 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
487 if (status < 0)
490 return status;
525 int status;
529 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
530 if (status < 0) {
531 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
532 return status;
555 int status;
565 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
566 if (status < 0)
570 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
571 if (status < 0)
576 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
577 if (status < 0)
594 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
595 if (status < 0)
600 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
601 if (status < 0)
608 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
609 if (status < 0)
619 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
620 if (status < 0)
622 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
623 if (status < 0)
672 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
673 if (status < 0)
675 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
676 if (status < 0)
678 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
679 if (status < 0)
681 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
682 if (status < 0)
684 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
685 if (status < 0)
695 return status;
700 int status = 0;
713 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
714 if (status < 0)
723 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
724 if (status < 0)
727 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
728 if (status < 0)
734 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
735 if (status < 0)
741 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
742 if (status < 0)
748 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
749 if (status < 0)
765 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
766 if (status < 0)
769 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
770 if (status < 0)
776 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
777 if (status < 0)
782 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
783 if (status < 0)
793 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
794 if (status < 0)
800 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
801 if (status < 0)
816 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
817 if (status < 0)
820 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
821 if (status < 0)
827 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
828 if (status < 0)
834 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
835 if (status < 0)
841 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
842 if (status < 0)
847 return status;
852 int status = 0;
857 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
859 if (status >= 0) {
887 return status;
918 int i, status = 0;
949 status = WriteBlock(state, Address, BlockSize,
951 if (status < 0)
957 return status;
963 int status;
965 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
966 if (status < 0)
967 return status;
972 status = -1;
975 status = Read16(state, HI_RA_RAM_SRV_CMD__A, NULL, 0);
976 } while (status != 0);
978 if (status >= 0)
979 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
980 return status;
985 int status = 0;
998 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
1001 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL);
1003 return status;
1016 int status;
1019 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1021 if (status == 0)
1022 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL);
1025 return status;
1048 int status;
1060 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1061 if (status < 0)
1063 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1064 if (status < 0)
1066 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1067 if (status < 0)
1069 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1070 if (status < 0)
1072 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1073 if (status < 0)
1076 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1077 if (status < 0)
1082 if (status >= 0) {
1086 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1088 if (status < 0)
1095 return status;
1102 int status;
1106 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1110 return status;
1135 int status = 0;
1144 status |= Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1145 status |= Write16(state, CC_REG_PLL_MODE__A,
1148 status |= Write16(state, CC_REG_REF_DIVIDE__A,
1150 status |= Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL,
1152 status |= Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1154 return status;
1159 int status = 0;
1162 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1164 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1166 if (!(status < 0))
1167 status = WriteTable(state, state->m_ResetECRAM);
1168 if (!(status < 0))
1169 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1170 return status;
1177 int status;
1184 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1185 if (status < 0)
1189 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1190 if (status < 0)
1194 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1195 if (status < 0)
1199 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1200 if (status < 0)
1205 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1206 if (status < 0)
1212 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1213 if (status < 0)
1217 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1218 if (status < 0)
1222 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1223 if (status < 0)
1227 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1228 if (status < 0)
1233 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1234 if (status < 0)
1238 return status;
1243 int status;
1246 status = WriteTable(state, state->m_InitFE_1);
1247 if (status < 0)
1251 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1256 status = SetCfgPga(state, 0);
1258 status =
1264 if (status < 0)
1266 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1267 if (status < 0)
1269 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1270 if (status < 0)
1273 status = WriteTable(state, state->m_InitFE_2);
1274 if (status < 0)
1279 return status;
1296 int status = Read16(state, SC_RA_RAM_CMD__A, NULL, 0);
1297 if (status == 0)
1298 return status;
1305 int status = 0, ret;
1308 status = Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1309 if (status < 0)
1310 return status;
1318 status = -1;
1321 return status;
1327 int ret, status = 0;
1334 status = -1;
1338 status |= Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1339 status |= Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1340 status |= Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1345 return status;
1351 int status;
1355 status = SC_WaitForReady(state);
1356 if (status < 0)
1358 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1359 if (status < 0)
1361 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1362 if (status < 0)
1364 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1365 if (status < 0)
1368 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1369 if (status < 0)
1373 return status;
1379 int status = 0;
1383 status = SC_WaitForReady(state);
1384 if (status < 0)
1386 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1387 if (status < 0)
1389 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1390 if (status < 0)
1394 return status;
1400 int status;
1472 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1473 if (status < 0)
1475 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1476 if (status < 0)
1478 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1479 if (status < 0)
1481 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1482 if (status < 0)
1485 return status;
1490 int status = 0;
1494 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1495 if (status < 0)
1498 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1499 if (status < 0)
1527 status = -1;
1533 if (status < 0)
1534 return status;
1579 return status;
1584 int status;
1598 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
1599 if (status < 0)
1601 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
1602 if (status < 0)
1659 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1660 if (status < 0)
1664 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1665 if (status < 0)
1671 return status;
1676 int status;
1684 status = DRX_GetLockStatus(state, &lock);
1685 if (status < 0)
1689 status = StopOC(state);
1690 if (status < 0)
1695 status = ConfigureMPEGOutput(state, 0);
1696 if (status < 0)
1701 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1702 if (status < 0)
1705 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1706 if (status < 0)
1708 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1709 if (status < 0)
1713 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1714 if (status < 0)
1716 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1717 if (status < 0)
1719 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1720 if (status < 0)
1722 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1723 if (status < 0)
1725 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1726 if (status < 0)
1728 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1729 if (status < 0)
1731 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1732 if (status < 0)
1737 return status;
1743 int status;
1747 status = -1;
1752 status = 0;
1757 status = -1;
1763 status = WriteTable(state, state->m_InitDiversityFront);
1766 status = WriteTable(state, state->m_InitDiversityEnd);
1772 status = WriteTable(state, state->m_DisableDiversity);
1777 if (!status)
1779 return status;
1785 int status = 0;
1790 status = WriteTable(state, state->m_StartDiversityFront);
1791 if (status < 0)
1794 status = WriteTable(state, state->m_StartDiversityEnd);
1795 if (status < 0)
1798 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1799 if (status < 0)
1802 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1803 if (status < 0)
1807 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1808 if (status < 0)
1816 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1817 if (status < 0)
1821 return status;
1866 int status = 0;
1869 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1870 if (status < 0)
1876 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1877 if (status < 0)
1880 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1881 if (status < 0)
1885 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1886 if (status < 0)
1888 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1889 if (status < 0)
1894 return status;
1900 int status;
1930 status = ResetECOD(state);
1931 if (status < 0)
1934 status = InitSC(state);
1935 if (status < 0)
1938 status = InitFT(state);
1939 if (status < 0)
1941 status = InitCP(state);
1942 if (status < 0)
1944 status = InitCE(state);
1945 if (status < 0)
1947 status = InitEQ(state);
1948 if (status < 0)
1950 status = InitSC(state);
1951 if (status < 0)
1957 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1958 if (status < 0)
1960 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1961 if (status < 0)
1973 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1974 if (status < 0)
1984 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1985 if (status < 0)
2018 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2019 if (status < 0)
2021 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2022 if (status < 0)
2048 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2049 if (status < 0)
2051 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2052 if (status < 0)
2077 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2078 if (status < 0)
2080 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2081 if (status < 0)
2109 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2110 if (status < 0)
2112 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2113 if (status < 0)
2136 if (status < 0)
2146 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2147 if (status < 0)
2149 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2150 if (status < 0)
2152 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2153 if (status < 0)
2155 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2156 if (status < 0)
2158 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2159 if (status < 0)
2162 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2163 if (status < 0)
2165 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2166 if (status < 0)
2168 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2169 if (status < 0)
2171 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2172 if (status < 0)
2179 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2180 if (status < 0)
2182 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2183 if (status < 0)
2185 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2186 if (status < 0)
2188 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2189 if (status < 0)
2191 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2192 if (status < 0)
2195 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2196 if (status < 0)
2198 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2199 if (status < 0)
2201 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2202 if (status < 0)
2204 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2205 if (status < 0)
2213 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2214 if (status < 0)
2216 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2217 if (status < 0)
2219 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2220 if (status < 0)
2222 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2223 if (status < 0)
2225 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2226 if (status < 0)
2229 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2230 if (status < 0)
2232 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2233 if (status < 0)
2235 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2236 if (status < 0)
2238 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2239 if (status < 0)
2245 if (status < 0)
2253 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2257 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2265 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2273 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2278 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2283 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2288 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2291 if (status < 0)
2310 status = Write16(state,
2317 status = Write16(state,
2324 status = Write16(state,
2328 status = -EINVAL;
2330 if (status < 0)
2333 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2334 if (status < 0)
2339 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2340 if (status < 0)
2353 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2354 if (status < 0)
2358 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2359 if (status < 0)
2364 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2365 if (status < 0)
2376 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2377 if (status < 0)
2379 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2380 if (status < 0)
2390 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2391 if (status < 0)
2393 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2394 if (status < 0)
2405 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2406 if (status < 0)
2410 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2411 if (status < 0)
2414 status = StartOC(state);
2415 if (status < 0)
2419 status = StartDiversity(state);
2420 if (status < 0)
2427 return status;
2585 int status = 0;
2596 status = SetDeviceTypeId(state);
2597 if (status < 0)
2602 status = WriteTable(state, state->m_HiI2cPatch);
2603 if (status < 0)
2610 status = Write16(state, 0x43012D, 0x047f, 0);
2611 if (status < 0)
2615 status = HI_ResetCommand(state);
2616 if (status < 0)
2619 status = StopAllProcessors(state);
2620 if (status < 0)
2622 status = InitCC(state);
2623 if (status < 0)
2652 status = InitHI(state);
2653 if (status < 0)
2655 status = InitAtomicRead(state);
2656 if (status < 0)
2659 status = EnableAndResetMB(state);
2660 if (status < 0)
2663 status = ResetCEFR(state);
2664 if (status < 0)
2668 status = DownloadMicrocode(state, fw, fw_size);
2669 if (status < 0)
2672 status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2673 if (status < 0)
2686 status = InitFE(state);
2687 if (status < 0)
2689 status = InitFT(state);
2690 if (status < 0)
2692 status = InitCP(state);
2693 if (status < 0)
2695 status = InitCE(state);
2696 if (status < 0)
2698 status = InitEQ(state);
2699 if (status < 0)
2701 status = InitEC(state);
2702 if (status < 0)
2704 status = InitSC(state);
2705 if (status < 0)
2708 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2709 if (status < 0)
2711 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2712 if (status < 0)
2716 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2717 if (status < 0)
2719 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2720 if (status < 0)
2731 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2732 if (status < 0)
2735 status = StopOC(state);
2736 if (status < 0)
2741 status = 0;
2743 return status;
2753 /* Get status again, in case we have MPEG lock now */
2778 static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status)
2784 *status = 0;
2788 *status |= FE_HAS_LOCK;
2791 *status |= FE_HAS_LOCK;
2794 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2796 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;