Lines Matching refs:hi_cmd
2107 struct drxj_hi_cmd hi_cmd;
2118 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY;
2119 hi_cmd.param1 =
2122 hi_cmd.param2 =
2124 hi_cmd.param3 = (u16) ((datasize / 2) - 1);
2126 hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE;
2128 hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ;
2129 hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) +
2131 hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr);
2145 rc = hi_command(dev_addr, &hi_cmd, &dummy);
2236 struct drxj_hi_cmd hi_cmd;
2242 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG;
2243 hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
2244 hi_cmd.param2 = ext_attr->hi_cfg_timing_div;
2245 hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay;
2246 hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key;
2247 hi_cmd.param5 = ext_attr->hi_cfg_ctrl;
2248 hi_cmd.param6 = ext_attr->hi_cfg_transmit;
2250 rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
3885 struct drxj_hi_cmd hi_cmd;
3892 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL;
3893 hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
3895 hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED;
3897 hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN;
3899 return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);