Lines Matching refs:data
339 /* Magic word for checking correct Endianness of microcode data */
536 u8 *data, u32 flags);
546 u16 *data, u32 flags);
550 u32 *data, u32 flags);
555 u8 *data, u32 flags);
559 u16 data, u32 flags);
563 u32 data, u32 flags);
901 * \brief Default audio data structure for DRK demodulator instance.
1003 * @addr: Destination address of the data in this block
1004 * @size: Size of the block data following this header counted in
1006 * @CRC: CRC value of the data block, only valid if CRC flag is
1395 * u8 *data, -- data to receive
1398 * Read block data from chip address. Because the chip is word oriented,
1401 * Make sure that the buffer to receive the data is large enough.
1404 * oriented, and the data read back is NOT translated to the endianness of
1409 * in that case: data read is in *data.
1417 u8 *data, u32 flags)
1435 ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
1486 rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data);
1490 data);
1492 data += todo;
1506 * u16 *data, -- data to receive
1509 * Read one 16-bit register or memory location. The data received back is
1514 * in that case: read data is at *data
1521 u16 *data, u32 flags)
1523 u8 buf[sizeof(*data)];
1526 if (!data)
1529 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1530 *data = buf[0] + (((u16) buf[1]) << 8);
1539 * u32 *data, -- data to receive
1542 * Read one 32-bit register or memory location. The data received back is
1547 * in that case: read data is at *data
1554 u32 *data, u32 flags)
1556 u8 buf[sizeof(*data)];
1559 if (!data)
1562 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1563 *data = (((u32) buf[0]) << 0) +
1575 * u8 *data, -- data to receive
1578 * Write block data to chip address. Because the chip is word oriented,
1582 * oriented, and the data being written is NOT translated from the endianness of
1594 u8 *data, u32 flags)
1613 ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1))
1657 4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
1658 (3) write address (4) write data etc...
1659 Address must be rewritten because HI is reset after data transport and
1688 memcpy(&buf[bufx], data, todo);
1689 /* write (address if can do and) data */
1701 data += todo;
1713 * u16 data, -- data to send
1716 * Write one 16-bit register or memory location. The data being written is
1727 u16 data, u32 flags)
1729 u8 buf[sizeof(data)];
1731 buf[0] = (u8) ((data >> 0) & 0xFF);
1732 buf[1] = (u8) ((data >> 8) & 0xFF);
1734 return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1743 * u16 wdata, -- data to send
1744 * u16 *rdata) -- data to receive back
1746 * Write 16-bit data, then read back the original contents of that location.
1749 * Before sending data, the data is converted to little endian. The
1750 * data received back is converted back to the target platform's endianness.
1757 * in that case: read back data is at *rdata
1786 * u32 data, -- data to send
1789 * Write one 32-bit register or memory location. The data being written is
1800 u32 data, u32 flags)
1802 u8 buf[sizeof(data)];
1804 buf[0] = (u8) ((data >> 0) & 0xFF);
1805 buf[1] = (u8) ((data >> 8) & 0xFF);
1806 buf[2] = (u8) ((data >> 16) & 0xFF);
1807 buf[3] = (u8) ((data >> 24) & 0xFF);
1809 return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1821 * \param rdata Buffer for data to read
1851 /* Write new data: triggers RMW */
1856 /* Read old data */
1898 * \param data
1907 u32 addr, u16 *data)
1975 0x0000, data);
1983 u16 *data, u32 flags)
1988 if ((dev_addr == NULL) || (data == NULL))
1992 stat = drxj_dap_read_aud_reg16(dev_addr, addr, data);
1994 stat = drxdap_fasi_read_reg16(dev_addr, addr, data, flags);
2005 * \param data
2014 u32 addr, u16 data)
2036 data, &tr_status);
2061 u16 data, u32 flags)
2070 stat = drxj_dap_write_aud_reg16(dev_addr, addr, data);
2073 addr, data, flags);
2080 /* Free data ram in SIO HI */
2094 * \param datasize size of data buffer in bytes
2095 * \param data pointer to data buffer
2105 u8 *data, bool read_flag)
2114 if (!data || !dev_addr || ((datasize % 2)) || ((datasize / 2) > 8))
2134 /* write data to buffer */
2137 word = ((u16) data[2 * i]);
2138 word += (((u16) data[(2 * i) + 1]) << 8);
2152 /* read data from buffer */
2161 data[2 * i] = (u8) (word & 0xFF);
2162 data[(2 * i) + 1] = (u8) (word >> 8);
2182 u32 *data, u32 flags)
2184 u8 buf[sizeof(*data)] = { 0 };
2188 if (!data)
2192 sizeof(*data), buf, true);
2205 *data = word;
2379 * \param demod pointer to demod data.
2680 u8 data = 0;
2694 data = 0;
2695 drxbsp_i2c_write_read(&wake_up_addr, 1, &data,
2702 &data)
2741 /* data mask for the output data byte */
2981 if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> clear ipr_mode[0] */
2983 } else { /* MPEG data output is serial -> set ipr_mode[0] */
3167 if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> set MD1 to MD7 to output mode */
3212 } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */
3669 * \param uio_data Pointer to data container for a certain UIO.
3714 /* use corresponding bit in io data output registar */
3725 /* write back to io data output register */
3753 /* use corresponding bit in io data output registar */
3764 /* write back to io data output register */
3792 /* use corresponding bit in io data output registar */
3803 /* write back to io data output register */
3832 /* use corresponding bit in io data output registar */
3843 /* write back to io data output register */
3922 u16 data = 0;
3934 rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0);
3940 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3946 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
4136 * \param datasize size of data buffer in bytes
4137 * \param data pointer to data buffer
4146 u8 *data, bool read_flag)
4154 if (!data || !dev_addr || (datasize % 2) || ((datasize / 2) > 16))
4168 (data[2 * i] | (data[(2 * i) + 1] << 8));
4187 /* read data from buffer */
4189 data[2 * i] = (u8) (scu_cmd.result[i + 2] & 0xFF);
4190 data[(2 * i) + 1] = (u8) (scu_cmd.result[i + 2] >> 8);
4210 u16 *data, u32 flags)
4216 if (!data)
4225 *data = word;
4238 u16 data, u32 flags)
4243 buf[0] = (u8) (data & 0xff);
4244 buf[1] = (u8) ((data >> 8) & 0xff);
4265 u16 data = 0;
4285 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0);
4290 if (data == 127)
4292 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0);
4297 if (data == 127)
4299 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0);
4304 if (data == 127)
4384 * \param channel pointer to channel data.
4404 u16 data = 0;
4738 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4743 data &= ~SCU_RAM_AGC_KI_DGAIN__M;
4744 data |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B);
4745 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4760 * \param channel pointer to channel data.
4860 * \retval 0 sig_strength contains valid data.
4862 * \retval -EIO Erroneous data, sig_strength contains invalid data.
4870 u16 data = 0;
4877 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0);
4883 last_pkt_err = data;
4888 if (data < last_pkt_err) {
4890 pkt_err += data;
4892 pkt_err += (data - last_pkt_err);
4895 last_pkt_err = data;
4942 u16 data = 0;
4948 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
4953 data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
4954 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
4961 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4966 data &= ~SCU_RAM_AGC_KI_RF__M;
4968 data |= (2 << SCU_RAM_AGC_KI_RF__B);
4970 data |= (5 << SCU_RAM_AGC_KI_RF__B);
4972 data |= (4 << SCU_RAM_AGC_KI_RF__B);
4975 data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
4977 data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
4978 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4985 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
4990 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
4991 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0);
5030 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5035 data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
5036 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5043 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5048 data &= ~SCU_RAM_AGC_KI_RF__M;
5050 data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
5052 data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
5053 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5069 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5074 data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
5075 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5082 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5087 data &= ~SCU_RAM_AGC_KI_RF__M;
5088 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5156 u16 data = 0;
5161 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5166 data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
5167 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5174 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5179 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5180 data &= ~SCU_RAM_AGC_KI_IF__M;
5182 data |= (3 << SCU_RAM_AGC_KI_IF__B);
5184 data |= (6 << SCU_RAM_AGC_KI_IF__B);
5186 data |= (5 << SCU_RAM_AGC_KI_IF__B);
5189 data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
5191 data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
5192 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5199 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
5204 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
5205 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0);
5249 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5254 data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
5255 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5262 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5267 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5268 data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5270 data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
5272 data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
5273 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5290 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5295 data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE);
5296 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5303 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5308 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5309 data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5310 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5358 u16 data = 0;
5365 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5371 data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE));
5373 data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
5374 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5399 * \param channel pointer to channel data.
5943 /* output data even when not locked */
6224 u16 data = 0;
6230 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0);
6235 packet_errors_mant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M;
6236 packet_errors_exp = (data & FEC_RS_NR_FAILURES_EXP__M)
6263 u16 data = 0;
6269 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0);
6277 bit_errors_mant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M;
6278 bit_errors_exp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M)
6307 u16 data = 0;
6310 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0);
6315 *ber = data;
6359 * \param channel pointer to channel data.
6481 struct drxj_data *ext_attr = NULL; /* Global data container for DRXJ specific data */
7854 * \param channel: pointer to channel data.
8685 u16 data = 0;
8730 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8735 data = (data & 0xfff9);
8736 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8741 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8774 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8779 equ_mode = data;
8780 data = (data & 0xfff9);
8781 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8786 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8793 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8798 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8806 rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8811 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8818 data = equ_mode;
8819 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8824 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8864 * \param channel: pointer to channel data.
8883 u16 data = 0;
8916 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8921 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8934 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8939 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0);
8974 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8979 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
9012 * \param channel: pointer to channel data.
9096 * \param channel: pointer to channel data.
9374 * \param u16-t Pointer to signal strength data; range 0, .. , 100.
9376 * \retval 0 sig_strength contains valid data.
9378 * \retval -EIO Erroneous data, sig_strength contains invalid data.
9454 * \param sig_quality Pointer to signal quality data.
9456 * \retval 0 sig_quality contains valid data.
9458 * \retval -EIO Erroneous data, sig_quality contains invalid data.
9500 /* Get the RS error data */
9626 /* fill signal quality data structure */
9721 The shadow settings will be stored in the device specific data container.
9876 u16 data = 0;
9879 rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0);
9885 data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON));
9887 data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON);
9888 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0);
10035 /* set frequency, spectrum inversion and data rate */
10039 /* 1-data rate;2-frequency */
10438 * \param channel Pointer to channel data.
10671 * \param sig_quality Pointer to signal quality data.
10673 * \retval 0 sig_quality contains valid data.
10675 * \retval -EIO Erroneous data, sig_quality contains invalid data.
11510 /* Stamp driver version number in SCU data RAM in BCD code
11546 /* refresh the audio data structure with default */
11610 * drx_u_code_compute_crc - Compute CRC of block of microcode data.
11611 * @block_data: Pointer to microcode data.
11726 * @mc_info: Pointer to information about microcode data.
11782 mc_data_init = demod->firmware->data;
11786 /* Check data */
11827 - data larger than 64Kb
11834 /* Wrong data ! */
12323 /* setup the demod data */