Lines Matching refs:rc
1376 pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
1421 int rc;
1483 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf,
1485 if (rc == 0)
1486 rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data);
1489 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo,
1495 } while (datasize && rc == 0);
1497 return rc;
1524 int rc;
1529 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1531 return rc;
1557 int rc;
1562 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1566 return rc;
1767 int rc = -EIO;
1773 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW);
1774 if (rc == 0)
1775 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0);
1778 return rc;
1840 int rc;
1846 rc = drxdap_fasi_write_reg16(dev_addr,
1850 if (rc == 0) {
1852 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata,
1855 if (rc == 0) {
1857 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata,
1860 if (rc == 0) {
1862 rc = drxdap_fasi_write_reg16(dev_addr,
1867 return rc;
2108 int rc;
2145 rc = hi_command(dev_addr, &hi_cmd, &dummy);
2146 if (rc != 0) {
2147 pr_err("error %d\n", rc);
2154 rc = drxj_dap_read_reg16(dev_addr,
2157 if (rc) {
2158 pr_err("error %d\n", rc);
2169 return rc;
2185 int rc;
2191 rc = drxj_dap_atomic_read_write_block(dev_addr, addr,
2194 if (rc < 0)
2207 return rc;
2238 int rc;
2250 rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
2251 if (rc != 0) {
2252 pr_err("error %d\n", rc);
2262 return rc;
2282 int rc;
2289 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0);
2290 if (rc != 0) {
2291 pr_err("error %d\n", rc);
2294 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0);
2295 if (rc != 0) {
2296 pr_err("error %d\n", rc);
2299 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0);
2300 if (rc != 0) {
2301 pr_err("error %d\n", rc);
2304 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0);
2305 if (rc != 0) {
2306 pr_err("error %d\n", rc);
2311 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);
2312 if (rc != 0) {
2313 pr_err("error %d\n", rc);
2316 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0);
2317 if (rc != 0) {
2318 pr_err("error %d\n", rc);
2332 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0);
2333 if (rc != 0) {
2334 pr_err("error %d\n", rc);
2355 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0);
2356 if (rc != 0) {
2357 pr_err("error %d\n", rc);
2363 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0);
2364 if (rc != 0) {
2365 pr_err("error %d\n", rc);
2373 return rc;
2394 int rc;
2401 rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0);
2402 if (rc != 0) {
2403 pr_err("error %d\n", rc);
2435 rc = hi_cfg_command(demod);
2436 if (rc != 0) {
2437 pr_err("error %d\n", rc);
2444 return rc;
2481 int rc;
2487 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2488 if (rc != 0) {
2489 pr_err("error %d\n", rc);
2492 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0);
2493 if (rc != 0) {
2494 pr_err("error %d\n", rc);
2497 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2498 if (rc != 0) {
2499 pr_err("error %d\n", rc);
2527 rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0);
2528 if (rc != 0) {
2529 pr_err("error %d\n", rc);
2536 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2537 if (rc != 0) {
2538 pr_err("error %d\n", rc);
2541 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0);
2542 if (rc != 0) {
2543 pr_err("error %d\n", rc);
2547 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2548 if (rc != 0) {
2549 pr_err("error %d\n", rc);
2660 return rc;
2733 int rc;
2769 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0);
2770 if (rc != 0) {
2771 pr_err("error %d\n", rc);
2776 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0);
2777 if (rc != 0) {
2778 pr_err("error %d\n", rc);
2781 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0);
2782 if (rc != 0) {
2783 pr_err("error %d\n", rc);
2786 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0);
2787 if (rc != 0) {
2788 pr_err("error %d\n", rc);
2791 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0);
2792 if (rc != 0) {
2793 pr_err("error %d\n", rc);
2796 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0);
2797 if (rc != 0) {
2798 pr_err("error %d\n", rc);
2801 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0);
2802 if (rc != 0) {
2803 pr_err("error %d\n", rc);
2807 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0);
2808 if (rc != 0) {
2809 pr_err("error %d\n", rc);
2813 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0);
2814 if (rc != 0) {
2815 pr_err("error %d\n", rc);
2846 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);
2847 if (rc != 0) {
2848 pr_err("error %d\n", rc);
2851 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0);
2852 if (rc != 0) {
2853 pr_err("error %d\n", rc);
2856 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0);
2857 if (rc != 0) {
2858 pr_err("error %d\n", rc);
2861 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0);
2862 if (rc != 0) {
2863 pr_err("error %d\n", rc);
2866 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0);
2867 if (rc != 0) {
2868 pr_err("error %d\n", rc);
2872 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0);
2873 if (rc != 0) {
2874 pr_err("error %d\n", rc);
2878 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0);
2879 if (rc != 0) {
2880 pr_err("error %d\n", rc);
2884 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0);
2885 if (rc != 0) {
2886 pr_err("error %d\n", rc);
2889 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0);
2890 if (rc != 0) {
2891 pr_err("error %d\n", rc);
2900 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
2901 if (rc != 0) {
2902 pr_err("error %d\n", rc);
2905 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0);
2906 if (rc != 0) {
2907 pr_err("error %d\n", rc);
3062 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0);
3063 if (rc != 0) {
3064 pr_err("error %d\n", rc);
3067 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0);
3068 if (rc != 0) {
3069 pr_err("error %d\n", rc);
3072 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0);
3073 if (rc != 0) {
3074 pr_err("error %d\n", rc);
3077 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0);
3078 if (rc != 0) {
3079 pr_err("error %d\n", rc);
3082 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0);
3083 if (rc != 0) {
3084 pr_err("error %d\n", rc);
3089 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0);
3090 if (rc != 0) {
3091 pr_err("error %d\n", rc);
3096 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0);
3097 if (rc != 0) {
3098 pr_err("error %d\n", rc);
3101 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0);
3102 if (rc != 0) {
3103 pr_err("error %d\n", rc);
3108 rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0);
3109 if (rc != 0) {
3110 pr_err("error %d\n", rc);
3115 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0);
3116 if (rc != 0) {
3117 pr_err("error %d\n", rc);
3120 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0);
3121 if (rc != 0) {
3122 pr_err("error %d\n", rc);
3125 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0);
3126 if (rc != 0) {
3127 pr_err("error %d\n", rc);
3133 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3134 if (rc != 0) {
3135 pr_err("error %d\n", rc);
3139 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0);
3140 if (rc != 0) {
3141 pr_err("error %d\n", rc);
3144 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0);
3145 if (rc != 0) {
3146 pr_err("error %d\n", rc);
3149 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0);
3150 if (rc != 0) {
3151 pr_err("error %d\n", rc);
3154 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0);
3155 if (rc != 0) {
3156 pr_err("error %d\n", rc);
3162 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3163 if (rc != 0) {
3164 pr_err("error %d\n", rc);
3172 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3173 if (rc != 0) {
3174 pr_err("error %d\n", rc);
3177 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0);
3178 if (rc != 0) {
3179 pr_err("error %d\n", rc);
3182 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0);
3183 if (rc != 0) {
3184 pr_err("error %d\n", rc);
3187 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0);
3188 if (rc != 0) {
3189 pr_err("error %d\n", rc);
3192 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0);
3193 if (rc != 0) {
3194 pr_err("error %d\n", rc);
3197 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0);
3198 if (rc != 0) {
3199 pr_err("error %d\n", rc);
3202 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0);
3203 if (rc != 0) {
3204 pr_err("error %d\n", rc);
3207 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0);
3208 if (rc != 0) {
3209 pr_err("error %d\n", rc);
3213 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3214 if (rc != 0) {
3215 pr_err("error %d\n", rc);
3218 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3219 if (rc != 0) {
3220 pr_err("error %d\n", rc);
3223 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3224 if (rc != 0) {
3225 pr_err("error %d\n", rc);
3228 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3229 if (rc != 0) {
3230 pr_err("error %d\n", rc);
3233 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3234 if (rc != 0) {
3235 pr_err("error %d\n", rc);
3238 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3239 if (rc != 0) {
3240 pr_err("error %d\n", rc);
3243 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3244 if (rc != 0) {
3245 pr_err("error %d\n", rc);
3250 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3251 if (rc != 0) {
3252 pr_err("error %d\n", rc);
3256 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3257 if (rc != 0) {
3258 pr_err("error %d\n", rc);
3263 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3264 if (rc != 0) {
3265 pr_err("error %d\n", rc);
3269 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0);
3270 if (rc != 0) {
3271 pr_err("error %d\n", rc);
3274 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0);
3275 if (rc != 0) {
3276 pr_err("error %d\n", rc);
3279 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0);
3280 if (rc != 0) {
3281 pr_err("error %d\n", rc);
3284 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0);
3285 if (rc != 0) {
3286 pr_err("error %d\n", rc);
3289 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0);
3290 if (rc != 0) {
3291 pr_err("error %d\n", rc);
3294 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3295 if (rc != 0) {
3296 pr_err("error %d\n", rc);
3299 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3300 if (rc != 0) {
3301 pr_err("error %d\n", rc);
3304 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3305 if (rc != 0) {
3306 pr_err("error %d\n", rc);
3309 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3310 if (rc != 0) {
3311 pr_err("error %d\n", rc);
3314 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3315 if (rc != 0) {
3316 pr_err("error %d\n", rc);
3319 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3320 if (rc != 0) {
3321 pr_err("error %d\n", rc);
3324 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3325 if (rc != 0) {
3326 pr_err("error %d\n", rc);
3330 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3331 if (rc != 0) {
3332 pr_err("error %d\n", rc);
3336 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3337 if (rc != 0) {
3338 pr_err("error %d\n", rc);
3348 return rc;
3375 int rc;
3383 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0);
3384 if (rc != 0) {
3385 pr_err("error %d\n", rc);
3388 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
3389 if (rc != 0) {
3390 pr_err("error %d\n", rc);
3393 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0);
3394 if (rc != 0) {
3395 pr_err("error %d\n", rc);
3413 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0);
3414 if (rc != 0) {
3415 pr_err("error %d\n", rc);
3418 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0);
3419 if (rc != 0) {
3420 pr_err("error %d\n", rc);
3423 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0);
3424 if (rc != 0) {
3425 pr_err("error %d\n", rc);
3431 return rc;
3448 int rc;
3454 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0);
3455 if (rc != 0) {
3456 pr_err("error %d\n", rc);
3466 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0);
3467 if (rc != 0) {
3468 pr_err("error %d\n", rc);
3474 return rc;
3492 int rc;
3501 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0);
3502 if (rc != 0) {
3503 pr_err("error %d\n", rc);
3509 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0);
3510 if (rc != 0) {
3511 pr_err("error %d\n", rc);
3518 return rc;
3538 int rc;
3546 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3547 if (rc != 0) {
3548 pr_err("error %d\n", rc);
3566 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0);
3567 if (rc != 0) {
3568 pr_err("error %d\n", rc);
3589 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0);
3590 if (rc != 0) {
3591 pr_err("error %d\n", rc);
3613 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0);
3614 if (rc != 0) {
3615 pr_err("error %d\n", rc);
3635 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0);
3636 if (rc != 0) {
3637 pr_err("error %d\n", rc);
3654 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3655 if (rc != 0) {
3656 pr_err("error %d\n", rc);
3662 return rc;
3676 int rc;
3686 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3687 if (rc != 0) {
3688 pr_err("error %d\n", rc);
3708 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);
3709 if (rc != 0) {
3710 pr_err("error %d\n", rc);
3715 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3716 if (rc != 0) {
3717 pr_err("error %d\n", rc);
3726 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3727 if (rc != 0) {
3728 pr_err("error %d\n", rc);
3747 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);
3748 if (rc != 0) {
3749 pr_err("error %d\n", rc);
3754 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3755 if (rc != 0) {
3756 pr_err("error %d\n", rc);
3765 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3766 if (rc != 0) {
3767 pr_err("error %d\n", rc);
3786 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0);
3787 if (rc != 0) {
3788 pr_err("error %d\n", rc);
3793 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0);
3794 if (rc != 0) {
3795 pr_err("error %d\n", rc);
3804 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0);
3805 if (rc != 0) {
3806 pr_err("error %d\n", rc);
3826 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0);
3827 if (rc != 0) {
3828 pr_err("error %d\n", rc);
3833 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3834 if (rc != 0) {
3835 pr_err("error %d\n", rc);
3844 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3845 if (rc != 0) {
3846 pr_err("error %d\n", rc);
3856 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3857 if (rc != 0) {
3858 pr_err("error %d\n", rc);
3864 return rc;
3921 int rc;
3928 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3929 if (rc != 0) {
3930 pr_err("error %d\n", rc);
3934 rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0);
3935 if (rc != 0) {
3936 pr_err("error %d\n", rc);
3940 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3941 if (rc != 0) {
3942 pr_err("error %d\n", rc);
3946 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3947 if (rc != 0) {
3948 pr_err("error %d\n", rc);
3954 rc = ctrl_set_uio_cfg(demod, &uio_cfg);
3955 if (rc != 0) {
3956 pr_err("error %d\n", rc);
3959 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0);
3960 if (rc != 0) {
3961 pr_err("error %d\n", rc);
3964 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0);
3965 if (rc != 0) {
3966 pr_err("error %d\n", rc);
3971 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3972 if (rc != 0) {
3973 pr_err("error %d\n", rc);
3979 return rc;
3984 int rc;
3993 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
3994 if (rc != 0) {
3995 pr_err("error %d\n", rc);
4003 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0);
4004 if (rc != 0) {
4005 pr_err("error %d\n", rc);
4010 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);
4011 if (rc != 0) {
4012 pr_err("error %d\n", rc);
4017 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);
4018 if (rc != 0) {
4019 pr_err("error %d\n", rc);
4024 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);
4025 if (rc != 0) {
4026 pr_err("error %d\n", rc);
4031 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);
4032 if (rc != 0) {
4033 pr_err("error %d\n", rc);
4044 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0);
4045 if (rc != 0) {
4046 pr_err("error %d\n", rc);
4053 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
4054 if (rc != 0) {
4055 pr_err("error %d\n", rc);
4072 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0);
4073 if (rc != 0) {
4074 pr_err("error %d\n", rc);
4079 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);
4080 if (rc != 0) {
4081 pr_err("error %d\n", rc);
4086 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);
4087 if (rc != 0) {
4088 pr_err("error %d\n", rc);
4093 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);
4094 if (rc != 0) {
4095 pr_err("error %d\n", rc);
4128 return rc;
4149 int rc;
4179 rc = scu_command(dev_addr, &scu_cmd);
4180 if (rc != 0) {
4181 pr_err("error %d\n", rc);
4197 return rc;
4213 int rc;
4219 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true);
4220 if (rc < 0)
4221 return rc;
4227 return rc;
4241 int rc;
4246 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false);
4248 return rc;
4264 int rc;
4270 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0);
4271 if (rc != 0) {
4272 pr_err("error %d\n", rc);
4275 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0);
4276 if (rc != 0) {
4277 pr_err("error %d\n", rc);
4285 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0);
4286 if (rc != 0) {
4287 pr_err("error %d\n", rc);
4292 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0);
4293 if (rc != 0) {
4294 pr_err("error %d\n", rc);
4299 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0);
4300 if (rc != 0) {
4301 pr_err("error %d\n", rc);
4309 return rc;
4327 int rc;
4332 rc = adc_sync_measurement(demod, &count);
4333 if (rc != 0) {
4334 pr_err("error %d\n", rc);
4342 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0);
4343 if (rc != 0) {
4344 pr_err("error %d\n", rc);
4349 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0);
4350 if (rc != 0) {
4351 pr_err("error %d\n", rc);
4355 rc = adc_sync_measurement(demod, &count);
4356 if (rc != 0) {
4357 pr_err("error %d\n", rc);
4368 return rc;
4394 int rc;
4428 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4429 if (rc != 0) {
4430 pr_err("error %d\n", rc);
4433 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4434 if (rc != 0) {
4435 pr_err("error %d\n", rc);
4438 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4439 if (rc != 0) {
4440 pr_err("error %d\n", rc);
4443 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4444 if (rc != 0) {
4445 pr_err("error %d\n", rc);
4448 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4449 if (rc != 0) {
4450 pr_err("error %d\n", rc);
4453 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4454 if (rc != 0) {
4455 pr_err("error %d\n", rc);
4458 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4459 if (rc != 0) {
4460 pr_err("error %d\n", rc);
4463 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4464 if (rc != 0) {
4465 pr_err("error %d\n", rc);
4468 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4469 if (rc != 0) {
4470 pr_err("error %d\n", rc);
4473 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4474 if (rc != 0) {
4475 pr_err("error %d\n", rc);
4478 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0);
4479 if (rc != 0) {
4480 pr_err("error %d\n", rc);
4483 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0);
4484 if (rc != 0) {
4485 pr_err("error %d\n", rc);
4488 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0);
4489 if (rc != 0) {
4490 pr_err("error %d\n", rc);
4511 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4512 if (rc != 0) {
4513 pr_err("error %d\n", rc);
4516 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4517 if (rc != 0) {
4518 pr_err("error %d\n", rc);
4521 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4522 if (rc != 0) {
4523 pr_err("error %d\n", rc);
4526 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4527 if (rc != 0) {
4528 pr_err("error %d\n", rc);
4531 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4532 if (rc != 0) {
4533 pr_err("error %d\n", rc);
4536 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4537 if (rc != 0) {
4538 pr_err("error %d\n", rc);
4541 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4542 if (rc != 0) {
4543 pr_err("error %d\n", rc);
4546 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4547 if (rc != 0) {
4548 pr_err("error %d\n", rc);
4551 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4552 if (rc != 0) {
4553 pr_err("error %d\n", rc);
4556 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4557 if (rc != 0) {
4558 pr_err("error %d\n", rc);
4563 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0);
4564 if (rc != 0) {
4565 pr_err("error %d\n", rc);
4569 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0);
4570 if (rc != 0) {
4571 pr_err("error %d\n", rc);
4575 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0);
4576 if (rc != 0) {
4577 pr_err("error %d\n", rc);
4587 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0);
4588 if (rc != 0) {
4589 pr_err("error %d\n", rc);
4592 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0);
4593 if (rc != 0) {
4594 pr_err("error %d\n", rc);
4597 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0);
4598 if (rc != 0) {
4599 pr_err("error %d\n", rc);
4602 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0);
4603 if (rc != 0) {
4604 pr_err("error %d\n", rc);
4607 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0);
4608 if (rc != 0) {
4609 pr_err("error %d\n", rc);
4612 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0);
4613 if (rc != 0) {
4614 pr_err("error %d\n", rc);
4617 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0);
4618 if (rc != 0) {
4619 pr_err("error %d\n", rc);
4622 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0);
4623 if (rc != 0) {
4624 pr_err("error %d\n", rc);
4627 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0);
4628 if (rc != 0) {
4629 pr_err("error %d\n", rc);
4632 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0);
4633 if (rc != 0) {
4634 pr_err("error %d\n", rc);
4637 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0);
4638 if (rc != 0) {
4639 pr_err("error %d\n", rc);
4642 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0);
4643 if (rc != 0) {
4644 pr_err("error %d\n", rc);
4647 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0);
4648 if (rc != 0) {
4649 pr_err("error %d\n", rc);
4652 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0);
4653 if (rc != 0) {
4654 pr_err("error %d\n", rc);
4657 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0);
4658 if (rc != 0) {
4659 pr_err("error %d\n", rc);
4662 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0);
4663 if (rc != 0) {
4664 pr_err("error %d\n", rc);
4667 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0);
4668 if (rc != 0) {
4669 pr_err("error %d\n", rc);
4672 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0);
4673 if (rc != 0) {
4674 pr_err("error %d\n", rc);
4677 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0);
4678 if (rc != 0) {
4679 pr_err("error %d\n", rc);
4682 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0);
4683 if (rc != 0) {
4684 pr_err("error %d\n", rc);
4687 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0);
4688 if (rc != 0) {
4689 pr_err("error %d\n", rc);
4692 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0);
4693 if (rc != 0) {
4694 pr_err("error %d\n", rc);
4697 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0);
4698 if (rc != 0) {
4699 pr_err("error %d\n", rc);
4702 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0);
4703 if (rc != 0) {
4704 pr_err("error %d\n", rc);
4707 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0);
4708 if (rc != 0) {
4709 pr_err("error %d\n", rc);
4712 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0);
4713 if (rc != 0) {
4714 pr_err("error %d\n", rc);
4726 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0);
4727 if (rc != 0) {
4728 pr_err("error %d\n", rc);
4731 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0);
4732 if (rc != 0) {
4733 pr_err("error %d\n", rc);
4738 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4739 if (rc != 0) {
4740 pr_err("error %d\n", rc);
4745 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4746 if (rc != 0) {
4747 pr_err("error %d\n", rc);
4753 return rc;
4770 int rc;
4841 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
4842 if (rc != 0) {
4843 pr_err("error %d\n", rc);
4851 return rc;
4867 int rc;
4877 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0);
4878 if (rc != 0) {
4879 pr_err("error %d\n", rc);
4899 return rc;
4920 int rc;
4948 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
4949 if (rc != 0) {
4950 pr_err("error %d\n", rc);
4954 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
4955 if (rc != 0) {
4956 pr_err("error %d\n", rc);
4961 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4962 if (rc != 0) {
4963 pr_err("error %d\n", rc);
4978 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4979 if (rc != 0) {
4980 pr_err("error %d\n", rc);
4985 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
4986 if (rc != 0) {
4987 pr_err("error %d\n", rc);
4991 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0);
4992 if (rc != 0) {
4993 pr_err("error %d\n", rc);
5008 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0);
5009 if (rc != 0) {
5010 pr_err("error %d\n", rc);
5013 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0);
5014 if (rc != 0) {
5015 pr_err("error %d\n", rc);
5021 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0);
5022 if (rc != 0) {
5023 pr_err("error %d\n", rc);
5030 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5031 if (rc != 0) {
5032 pr_err("error %d\n", rc);
5036 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5037 if (rc != 0) {
5038 pr_err("error %d\n", rc);
5043 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5044 if (rc != 0) {
5045 pr_err("error %d\n", rc);
5053 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5054 if (rc != 0) {
5055 pr_err("error %d\n", rc);
5060 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0);
5061 if (rc != 0) {
5062 pr_err("error %d\n", rc);
5069 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5070 if (rc != 0) {
5071 pr_err("error %d\n", rc);
5075 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5076 if (rc != 0) {
5077 pr_err("error %d\n", rc);
5082 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5083 if (rc != 0) {
5084 pr_err("error %d\n", rc);
5088 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5089 if (rc != 0) {
5090 pr_err("error %d\n", rc);
5117 return rc;
5136 int rc;
5161 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5162 if (rc != 0) {
5163 pr_err("error %d\n", rc);
5167 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5168 if (rc != 0) {
5169 pr_err("error %d\n", rc);
5174 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5175 if (rc != 0) {
5176 pr_err("error %d\n", rc);
5192 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5193 if (rc != 0) {
5194 pr_err("error %d\n", rc);
5199 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
5200 if (rc != 0) {
5201 pr_err("error %d\n", rc);
5205 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0);
5206 if (rc != 0) {
5207 pr_err("error %d\n", rc);
5222 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0);
5223 if (rc != 0) {
5224 pr_err("error %d\n", rc);
5227 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0);
5228 if (rc != 0) {
5229 pr_err("error %d\n", rc);
5233 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0);
5234 if (rc != 0) {
5235 pr_err("error %d\n", rc);
5238 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0);
5239 if (rc != 0) {
5240 pr_err("error %d\n", rc);
5249 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5250 if (rc != 0) {
5251 pr_err("error %d\n", rc);
5255 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5256 if (rc != 0) {
5257 pr_err("error %d\n", rc);
5262 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5263 if (rc != 0) {
5264 pr_err("error %d\n", rc);
5273 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5274 if (rc != 0) {
5275 pr_err("error %d\n", rc);
5280 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0);
5281 if (rc != 0) {
5282 pr_err("error %d\n", rc);
5290 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5291 if (rc != 0) {
5292 pr_err("error %d\n", rc);
5296 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5297 if (rc != 0) {
5298 pr_err("error %d\n", rc);
5303 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5304 if (rc != 0) {
5305 pr_err("error %d\n", rc);
5310 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5311 if (rc != 0) {
5312 pr_err("error %d\n", rc);
5321 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0);
5322 if (rc != 0) {
5323 pr_err("error %d\n", rc);
5346 return rc;
5360 int rc;
5365 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5366 if (rc != 0) {
5367 pr_err("error %d\n", rc);
5374 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5375 if (rc != 0) {
5376 pr_err("error %d\n", rc);
5382 return rc;
5412 int rc;
5425 rc = scu_command(dev_addr, &cmd_scu);
5426 if (rc != 0) {
5427 pr_err("error %d\n", rc);
5432 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5433 if (rc != 0) {
5434 pr_err("error %d\n", rc);
5437 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5438 if (rc != 0) {
5439 pr_err("error %d\n", rc);
5443 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
5444 if (rc != 0) {
5445 pr_err("error %d\n", rc);
5448 rc = set_iqm_af(demod, false);
5449 if (rc != 0) {
5450 pr_err("error %d\n", rc);
5454 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5455 if (rc != 0) {
5456 pr_err("error %d\n", rc);
5459 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5460 if (rc != 0) {
5461 pr_err("error %d\n", rc);
5464 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5465 if (rc != 0) {
5466 pr_err("error %d\n", rc);
5469 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5470 if (rc != 0) {
5471 pr_err("error %d\n", rc);
5474 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5475 if (rc != 0) {
5476 pr_err("error %d\n", rc);
5482 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
5483 if (rc != 0) {
5484 pr_err("error %d\n", rc);
5490 return rc;
5502 int rc;
5693 rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0);
5694 if (rc != 0) {
5695 pr_err("error %d\n", rc);
5698 rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0);
5699 if (rc != 0) {
5700 pr_err("error %d\n", rc);
5706 return rc;
5719 int rc;
5761 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5762 if (rc != 0) {
5763 pr_err("error %d\n", rc);
5766 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5767 if (rc != 0) {
5768 pr_err("error %d\n", rc);
5771 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5772 if (rc != 0) {
5773 pr_err("error %d\n", rc);
5776 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5777 if (rc != 0) {
5778 pr_err("error %d\n", rc);
5781 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5782 if (rc != 0) {
5783 pr_err("error %d\n", rc);
5786 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5787 if (rc != 0) {
5788 pr_err("error %d\n", rc);
5791 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5792 if (rc != 0) {
5793 pr_err("error %d\n", rc);
5804 rc = scu_command(dev_addr, &cmd_scu);
5805 if (rc != 0) {
5806 pr_err("error %d\n", rc);
5810 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0);
5811 if (rc != 0) {
5812 pr_err("error %d\n", rc);
5815 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0);
5816 if (rc != 0) {
5817 pr_err("error %d\n", rc);
5820 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0);
5821 if (rc != 0) {
5822 pr_err("error %d\n", rc);
5826 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);
5827 if (rc != 0) {
5828 pr_err("error %d\n", rc);
5831 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0);
5832 if (rc != 0) {
5833 pr_err("error %d\n", rc);
5836 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0);
5837 if (rc != 0) {
5838 pr_err("error %d\n", rc);
5842 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0);
5843 if (rc != 0) {
5844 pr_err("error %d\n", rc);
5847 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0);
5848 if (rc != 0) {
5849 pr_err("error %d\n", rc);
5852 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0);
5853 if (rc != 0) {
5854 pr_err("error %d\n", rc);
5857 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
5858 if (rc != 0) {
5859 pr_err("error %d\n", rc);
5862 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
5863 if (rc != 0) {
5864 pr_err("error %d\n", rc);
5867 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0);
5868 if (rc != 0) {
5869 pr_err("error %d\n", rc);
5872 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0);
5873 if (rc != 0) {
5874 pr_err("error %d\n", rc);
5877 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
5878 if (rc != 0) {
5879 pr_err("error %d\n", rc);
5882 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
5883 if (rc != 0) {
5884 pr_err("error %d\n", rc);
5888 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5889 if (rc != 0) {
5890 pr_err("error %d\n", rc);
5893 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5894 if (rc != 0) {
5895 pr_err("error %d\n", rc);
5899 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0);
5900 if (rc != 0) {
5901 pr_err("error %d\n", rc);
5904 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0);
5905 if (rc != 0) {
5906 pr_err("error %d\n", rc);
5909 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0);
5910 if (rc != 0) {
5911 pr_err("error %d\n", rc);
5914 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0);
5915 if (rc != 0) {
5916 pr_err("error %d\n", rc);
5919 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0);
5920 if (rc != 0) {
5921 pr_err("error %d\n", rc);
5924 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
5925 if (rc != 0) {
5926 pr_err("error %d\n", rc);
5931 rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0);
5932 if (rc != 0) {
5933 pr_err("error %d\n", rc);
5938 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
5939 if (rc != 0) {
5940 pr_err("error %d\n", rc);
5944 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0);
5945 if (rc != 0) {
5946 pr_err("error %d\n", rc);
5952 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
5953 if (rc != 0) {
5954 pr_err("error %d\n", rc);
5957 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0);
5958 if (rc != 0) {
5959 pr_err("error %d\n", rc);
5962 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
5963 if (rc != 0) {
5964 pr_err("error %d\n", rc);
5967 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0);
5968 if (rc != 0) {
5969 pr_err("error %d\n", rc);
5975 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
5976 if (rc != 0) {
5977 pr_err("error %d\n", rc);
5980 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0);
5981 if (rc != 0) {
5982 pr_err("error %d\n", rc);
5987 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0);
5988 if (rc != 0) {
5989 pr_err("error %d\n", rc);
5992 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0);
5993 if (rc != 0) {
5994 pr_err("error %d\n", rc);
5997 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0);
5998 if (rc != 0) {
5999 pr_err("error %d\n", rc);
6003 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0);
6004 if (rc != 0) {
6005 pr_err("error %d\n", rc);
6008 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0);
6009 if (rc != 0) {
6010 pr_err("error %d\n", rc);
6015 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0);
6016 if (rc != 0) {
6017 pr_err("error %d\n", rc);
6020 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6021 if (rc != 0) {
6022 pr_err("error %d\n", rc);
6025 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6026 if (rc != 0) {
6027 pr_err("error %d\n", rc);
6030 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6031 if (rc != 0) {
6032 pr_err("error %d\n", rc);
6036 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0);
6037 if (rc != 0) {
6038 pr_err("error %d\n", rc);
6043 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
6044 if (rc != 0) {
6045 pr_err("error %d\n", rc);
6051 rc = set_iqm_af(demod, true);
6052 if (rc != 0) {
6053 pr_err("error %d\n", rc);
6056 rc = adc_synchronization(demod);
6057 if (rc != 0) {
6058 pr_err("error %d\n", rc);
6062 rc = init_agc(demod);
6063 if (rc != 0) {
6064 pr_err("error %d\n", rc);
6067 rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);
6068 if (rc != 0) {
6069 pr_err("error %d\n", rc);
6072 rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);
6073 if (rc != 0) {
6074 pr_err("error %d\n", rc);
6083 rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg);
6084 if (rc != 0) {
6085 pr_err("error %d\n", rc);
6089 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));
6090 if (rc != 0) {
6091 pr_err("error %d\n", rc);
6096 rc = set_mpegtei_handling(demod);
6097 if (rc != 0) {
6098 pr_err("error %d\n", rc);
6101 rc = bit_reverse_mpeg_output(demod);
6102 if (rc != 0) {
6103 pr_err("error %d\n", rc);
6106 rc = set_mpeg_start_width(demod);
6107 if (rc != 0) {
6108 pr_err("error %d\n", rc);
6119 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6120 if (rc != 0) {
6121 pr_err("error %d\n", rc);
6134 rc = scu_command(dev_addr, &cmd_scu);
6135 if (rc != 0) {
6136 pr_err("error %d\n", rc);
6140 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0);
6141 if (rc != 0) {
6142 pr_err("error %d\n", rc);
6145 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0);
6146 if (rc != 0) {
6147 pr_err("error %d\n", rc);
6150 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0);
6151 if (rc != 0) {
6152 pr_err("error %d\n", rc);
6155 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0);
6156 if (rc != 0) {
6157 pr_err("error %d\n", rc);
6160 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0);
6161 if (rc != 0) {
6162 pr_err("error %d\n", rc);
6165 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0);
6166 if (rc != 0) {
6167 pr_err("error %d\n", rc);
6170 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0);
6171 if (rc != 0) {
6172 pr_err("error %d\n", rc);
6175 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0);
6176 if (rc != 0) {
6177 pr_err("error %d\n", rc);
6188 rc = scu_command(dev_addr, &cmd_scu);
6189 if (rc != 0) {
6190 pr_err("error %d\n", rc);
6194 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
6195 if (rc != 0) {
6196 pr_err("error %d\n", rc);
6199 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0);
6200 if (rc != 0) {
6201 pr_err("error %d\n", rc);
6204 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
6205 if (rc != 0) {
6206 pr_err("error %d\n", rc);
6212 return rc;
6223 int rc;
6230 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0);
6231 if (rc != 0) {
6232 pr_err("error %d\n", rc);
6251 return rc;
6262 int rc;
6269 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0);
6270 if (rc != 0) {
6271 pr_err("error %d\n", rc);
6296 return rc;
6308 int rc;
6310 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0);
6311 if (rc != 0) {
6312 pr_err("error %d\n", rc);
6328 int rc;
6331 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0);
6332 if (rc != 0) {
6333 pr_err("error %d\n", rc);
6341 return rc;
6370 int rc;
6381 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
6382 if (rc != 0) {
6383 pr_err("error %d\n", rc);
6386 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
6387 if (rc != 0) {
6388 pr_err("error %d\n", rc);
6398 rc = scu_command(dev_addr, &cmd_scu);
6399 if (rc != 0) {
6400 pr_err("error %d\n", rc);
6405 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
6406 if (rc != 0) {
6407 pr_err("error %d\n", rc);
6410 rc = set_iqm_af(demod, false);
6411 if (rc != 0) {
6412 pr_err("error %d\n", rc);
6416 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
6417 if (rc != 0) {
6418 pr_err("error %d\n", rc);
6421 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
6422 if (rc != 0) {
6423 pr_err("error %d\n", rc);
6426 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
6427 if (rc != 0) {
6428 pr_err("error %d\n", rc);
6431 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
6432 if (rc != 0) {
6433 pr_err("error %d\n", rc);
6436 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
6437 if (rc != 0) {
6438 pr_err("error %d\n", rc);
6446 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6447 if (rc != 0) {
6448 pr_err("error %d\n", rc);
6454 return rc;
6482 int rc;
6576 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0);
6577 if (rc != 0) {
6578 pr_err("error %d\n", rc);
6581 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0);
6582 if (rc != 0) {
6583 pr_err("error %d\n", rc);
6586 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0);
6587 if (rc != 0) {
6588 pr_err("error %d\n", rc);
6593 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6594 if (rc != 0) {
6595 pr_err("error %d\n", rc);
6598 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6599 if (rc != 0) {
6600 pr_err("error %d\n", rc);
6603 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6604 if (rc != 0) {
6605 pr_err("error %d\n", rc);
6650 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0);
6651 if (rc != 0) {
6652 pr_err("error %d\n", rc);
6655 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0);
6656 if (rc != 0) {
6657 pr_err("error %d\n", rc);
6666 return rc;
6680 int rc;
6698 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6699 if (rc != 0) {
6700 pr_err("error %d\n", rc);
6703 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6704 if (rc != 0) {
6705 pr_err("error %d\n", rc);
6709 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0);
6710 if (rc != 0) {
6711 pr_err("error %d\n", rc);
6714 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6715 if (rc != 0) {
6716 pr_err("error %d\n", rc);
6719 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0);
6720 if (rc != 0) {
6721 pr_err("error %d\n", rc);
6724 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0);
6725 if (rc != 0) {
6726 pr_err("error %d\n", rc);
6729 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0);
6730 if (rc != 0) {
6731 pr_err("error %d\n", rc);
6734 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0);
6735 if (rc != 0) {
6736 pr_err("error %d\n", rc);
6740 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6741 if (rc != 0) {
6742 pr_err("error %d\n", rc);
6745 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6746 if (rc != 0) {
6747 pr_err("error %d\n", rc);
6750 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6751 if (rc != 0) {
6752 pr_err("error %d\n", rc);
6756 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0);
6757 if (rc != 0) {
6758 pr_err("error %d\n", rc);
6761 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0);
6762 if (rc != 0) {
6763 pr_err("error %d\n", rc);
6766 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0);
6767 if (rc != 0) {
6768 pr_err("error %d\n", rc);
6771 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0);
6772 if (rc != 0) {
6773 pr_err("error %d\n", rc);
6776 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0);
6777 if (rc != 0) {
6778 pr_err("error %d\n", rc);
6781 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0);
6782 if (rc != 0) {
6783 pr_err("error %d\n", rc);
6786 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0);
6787 if (rc != 0) {
6788 pr_err("error %d\n", rc);
6792 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
6793 if (rc != 0) {
6794 pr_err("error %d\n", rc);
6797 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
6798 if (rc != 0) {
6799 pr_err("error %d\n", rc);
6802 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
6803 if (rc != 0) {
6804 pr_err("error %d\n", rc);
6807 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
6808 if (rc != 0) {
6809 pr_err("error %d\n", rc);
6812 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
6813 if (rc != 0) {
6814 pr_err("error %d\n", rc);
6817 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
6818 if (rc != 0) {
6819 pr_err("error %d\n", rc);
6822 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
6823 if (rc != 0) {
6824 pr_err("error %d\n", rc);
6827 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
6828 if (rc != 0) {
6829 pr_err("error %d\n", rc);
6832 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
6833 if (rc != 0) {
6834 pr_err("error %d\n", rc);
6837 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
6838 if (rc != 0) {
6839 pr_err("error %d\n", rc);
6842 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
6843 if (rc != 0) {
6844 pr_err("error %d\n", rc);
6847 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
6848 if (rc != 0) {
6849 pr_err("error %d\n", rc);
6852 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
6853 if (rc != 0) {
6854 pr_err("error %d\n", rc);
6857 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
6858 if (rc != 0) {
6859 pr_err("error %d\n", rc);
6862 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
6863 if (rc != 0) {
6864 pr_err("error %d\n", rc);
6867 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
6868 if (rc != 0) {
6869 pr_err("error %d\n", rc);
6872 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0);
6873 if (rc != 0) {
6874 pr_err("error %d\n", rc);
6877 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
6878 if (rc != 0) {
6879 pr_err("error %d\n", rc);
6882 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
6883 if (rc != 0) {
6884 pr_err("error %d\n", rc);
6887 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
6888 if (rc != 0) {
6889 pr_err("error %d\n", rc);
6893 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0);
6894 if (rc != 0) {
6895 pr_err("error %d\n", rc);
6901 return rc;
6915 int rc;
6933 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6934 if (rc != 0) {
6935 pr_err("error %d\n", rc);
6938 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6939 if (rc != 0) {
6940 pr_err("error %d\n", rc);
6944 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0);
6945 if (rc != 0) {
6946 pr_err("error %d\n", rc);
6949 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6950 if (rc != 0) {
6951 pr_err("error %d\n", rc);
6954 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
6955 if (rc != 0) {
6956 pr_err("error %d\n", rc);
6959 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0);
6960 if (rc != 0) {
6961 pr_err("error %d\n", rc);
6964 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
6965 if (rc != 0) {
6966 pr_err("error %d\n", rc);
6969 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
6970 if (rc != 0) {
6971 pr_err("error %d\n", rc);
6975 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6976 if (rc != 0) {
6977 pr_err("error %d\n", rc);
6980 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6981 if (rc != 0) {
6982 pr_err("error %d\n", rc);
6985 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6986 if (rc != 0) {
6987 pr_err("error %d\n", rc);
6991 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
6992 if (rc != 0) {
6993 pr_err("error %d\n", rc);
6996 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0);
6997 if (rc != 0) {
6998 pr_err("error %d\n", rc);
7001 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0);
7002 if (rc != 0) {
7003 pr_err("error %d\n", rc);
7006 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0);
7007 if (rc != 0) {
7008 pr_err("error %d\n", rc);
7011 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0);
7012 if (rc != 0) {
7013 pr_err("error %d\n", rc);
7016 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0);
7017 if (rc != 0) {
7018 pr_err("error %d\n", rc);
7021 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0);
7022 if (rc != 0) {
7023 pr_err("error %d\n", rc);
7027 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7028 if (rc != 0) {
7029 pr_err("error %d\n", rc);
7032 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7033 if (rc != 0) {
7034 pr_err("error %d\n", rc);
7037 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7038 if (rc != 0) {
7039 pr_err("error %d\n", rc);
7042 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
7043 if (rc != 0) {
7044 pr_err("error %d\n", rc);
7047 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7048 if (rc != 0) {
7049 pr_err("error %d\n", rc);
7052 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7053 if (rc != 0) {
7054 pr_err("error %d\n", rc);
7057 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
7058 if (rc != 0) {
7059 pr_err("error %d\n", rc);
7062 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
7063 if (rc != 0) {
7064 pr_err("error %d\n", rc);
7067 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7068 if (rc != 0) {
7069 pr_err("error %d\n", rc);
7072 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7073 if (rc != 0) {
7074 pr_err("error %d\n", rc);
7077 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7078 if (rc != 0) {
7079 pr_err("error %d\n", rc);
7082 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7083 if (rc != 0) {
7084 pr_err("error %d\n", rc);
7087 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7088 if (rc != 0) {
7089 pr_err("error %d\n", rc);
7092 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7093 if (rc != 0) {
7094 pr_err("error %d\n", rc);
7097 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7098 if (rc != 0) {
7099 pr_err("error %d\n", rc);
7102 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7103 if (rc != 0) {
7104 pr_err("error %d\n", rc);
7107 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0);
7108 if (rc != 0) {
7109 pr_err("error %d\n", rc);
7112 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7113 if (rc != 0) {
7114 pr_err("error %d\n", rc);
7117 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7118 if (rc != 0) {
7119 pr_err("error %d\n", rc);
7122 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0);
7123 if (rc != 0) {
7124 pr_err("error %d\n", rc);
7128 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0);
7129 if (rc != 0) {
7130 pr_err("error %d\n", rc);
7136 return rc;
7150 int rc;
7169 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7170 if (rc != 0) {
7171 pr_err("error %d\n", rc);
7174 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7175 if (rc != 0) {
7176 pr_err("error %d\n", rc);
7180 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0);
7181 if (rc != 0) {
7182 pr_err("error %d\n", rc);
7185 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7186 if (rc != 0) {
7187 pr_err("error %d\n", rc);
7190 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7191 if (rc != 0) {
7192 pr_err("error %d\n", rc);
7195 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0);
7196 if (rc != 0) {
7197 pr_err("error %d\n", rc);
7200 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7201 if (rc != 0) {
7202 pr_err("error %d\n", rc);
7205 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0);
7206 if (rc != 0) {
7207 pr_err("error %d\n", rc);
7211 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7212 if (rc != 0) {
7213 pr_err("error %d\n", rc);
7216 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7217 if (rc != 0) {
7218 pr_err("error %d\n", rc);
7221 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7222 if (rc != 0) {
7223 pr_err("error %d\n", rc);
7227 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
7228 if (rc != 0) {
7229 pr_err("error %d\n", rc);
7232 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0);
7233 if (rc != 0) {
7234 pr_err("error %d\n", rc);
7237 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0);
7238 if (rc != 0) {
7239 pr_err("error %d\n", rc);
7242 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0);
7243 if (rc != 0) {
7244 pr_err("error %d\n", rc);
7247 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0);
7248 if (rc != 0) {
7249 pr_err("error %d\n", rc);
7252 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0);
7253 if (rc != 0) {
7254 pr_err("error %d\n", rc);
7257 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0);
7258 if (rc != 0) {
7259 pr_err("error %d\n", rc);
7263 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7264 if (rc != 0) {
7265 pr_err("error %d\n", rc);
7268 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7269 if (rc != 0) {
7270 pr_err("error %d\n", rc);
7273 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7274 if (rc != 0) {
7275 pr_err("error %d\n", rc);
7278 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0);
7279 if (rc != 0) {
7280 pr_err("error %d\n", rc);
7283 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7284 if (rc != 0) {
7285 pr_err("error %d\n", rc);
7288 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7289 if (rc != 0) {
7290 pr_err("error %d\n", rc);
7293 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0);
7294 if (rc != 0) {
7295 pr_err("error %d\n", rc);
7298 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7299 if (rc != 0) {
7300 pr_err("error %d\n", rc);
7303 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7304 if (rc != 0) {
7305 pr_err("error %d\n", rc);
7308 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7309 if (rc != 0) {
7310 pr_err("error %d\n", rc);
7313 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7314 if (rc != 0) {
7315 pr_err("error %d\n", rc);
7318 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7319 if (rc != 0) {
7320 pr_err("error %d\n", rc);
7323 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7324 if (rc != 0) {
7325 pr_err("error %d\n", rc);
7328 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7329 if (rc != 0) {
7330 pr_err("error %d\n", rc);
7333 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7334 if (rc != 0) {
7335 pr_err("error %d\n", rc);
7338 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7339 if (rc != 0) {
7340 pr_err("error %d\n", rc);
7343 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0);
7344 if (rc != 0) {
7345 pr_err("error %d\n", rc);
7348 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7349 if (rc != 0) {
7350 pr_err("error %d\n", rc);
7353 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7354 if (rc != 0) {
7355 pr_err("error %d\n", rc);
7358 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
7359 if (rc != 0) {
7360 pr_err("error %d\n", rc);
7364 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0);
7365 if (rc != 0) {
7366 pr_err("error %d\n", rc);
7372 return rc;
7386 int rc;
7404 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7405 if (rc != 0) {
7406 pr_err("error %d\n", rc);
7409 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7410 if (rc != 0) {
7411 pr_err("error %d\n", rc);
7415 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7416 if (rc != 0) {
7417 pr_err("error %d\n", rc);
7420 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7421 if (rc != 0) {
7422 pr_err("error %d\n", rc);
7425 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7426 if (rc != 0) {
7427 pr_err("error %d\n", rc);
7430 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0);
7431 if (rc != 0) {
7432 pr_err("error %d\n", rc);
7435 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7436 if (rc != 0) {
7437 pr_err("error %d\n", rc);
7440 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
7441 if (rc != 0) {
7442 pr_err("error %d\n", rc);
7446 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7447 if (rc != 0) {
7448 pr_err("error %d\n", rc);
7451 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7452 if (rc != 0) {
7453 pr_err("error %d\n", rc);
7456 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7457 if (rc != 0) {
7458 pr_err("error %d\n", rc);
7462 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7463 if (rc != 0) {
7464 pr_err("error %d\n", rc);
7467 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0);
7468 if (rc != 0) {
7469 pr_err("error %d\n", rc);
7472 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0);
7473 if (rc != 0) {
7474 pr_err("error %d\n", rc);
7477 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0);
7478 if (rc != 0) {
7479 pr_err("error %d\n", rc);
7482 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0);
7483 if (rc != 0) {
7484 pr_err("error %d\n", rc);
7487 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0);
7488 if (rc != 0) {
7489 pr_err("error %d\n", rc);
7492 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0);
7493 if (rc != 0) {
7494 pr_err("error %d\n", rc);
7498 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7499 if (rc != 0) {
7500 pr_err("error %d\n", rc);
7503 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7504 if (rc != 0) {
7505 pr_err("error %d\n", rc);
7508 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7509 if (rc != 0) {
7510 pr_err("error %d\n", rc);
7513 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0);
7514 if (rc != 0) {
7515 pr_err("error %d\n", rc);
7518 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7519 if (rc != 0) {
7520 pr_err("error %d\n", rc);
7523 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7524 if (rc != 0) {
7525 pr_err("error %d\n", rc);
7528 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0);
7529 if (rc != 0) {
7530 pr_err("error %d\n", rc);
7533 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7534 if (rc != 0) {
7535 pr_err("error %d\n", rc);
7538 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7539 if (rc != 0) {
7540 pr_err("error %d\n", rc);
7543 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7544 if (rc != 0) {
7545 pr_err("error %d\n", rc);
7548 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7549 if (rc != 0) {
7550 pr_err("error %d\n", rc);
7553 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7554 if (rc != 0) {
7555 pr_err("error %d\n", rc);
7558 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7559 if (rc != 0) {
7560 pr_err("error %d\n", rc);
7563 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7564 if (rc != 0) {
7565 pr_err("error %d\n", rc);
7568 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7569 if (rc != 0) {
7570 pr_err("error %d\n", rc);
7573 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7574 if (rc != 0) {
7575 pr_err("error %d\n", rc);
7578 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0);
7579 if (rc != 0) {
7580 pr_err("error %d\n", rc);
7583 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7584 if (rc != 0) {
7585 pr_err("error %d\n", rc);
7588 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7589 if (rc != 0) {
7590 pr_err("error %d\n", rc);
7593 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7594 if (rc != 0) {
7595 pr_err("error %d\n", rc);
7599 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0);
7600 if (rc != 0) {
7601 pr_err("error %d\n", rc);
7607 return rc;
7621 int rc;
7639 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7640 if (rc != 0) {
7641 pr_err("error %d\n", rc);
7644 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7645 if (rc != 0) {
7646 pr_err("error %d\n", rc);
7650 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7651 if (rc != 0) {
7652 pr_err("error %d\n", rc);
7655 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7656 if (rc != 0) {
7657 pr_err("error %d\n", rc);
7660 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7661 if (rc != 0) {
7662 pr_err("error %d\n", rc);
7665 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0);
7666 if (rc != 0) {
7667 pr_err("error %d\n", rc);
7670 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7671 if (rc != 0) {
7672 pr_err("error %d\n", rc);
7675 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0);
7676 if (rc != 0) {
7677 pr_err("error %d\n", rc);
7681 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7682 if (rc != 0) {
7683 pr_err("error %d\n", rc);
7686 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0);
7687 if (rc != 0) {
7688 pr_err("error %d\n", rc);
7691 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7692 if (rc != 0) {
7693 pr_err("error %d\n", rc);
7697 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7698 if (rc != 0) {
7699 pr_err("error %d\n", rc);
7702 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0);
7703 if (rc != 0) {
7704 pr_err("error %d\n", rc);
7707 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0);
7708 if (rc != 0) {
7709 pr_err("error %d\n", rc);
7712 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0);
7713 if (rc != 0) {
7714 pr_err("error %d\n", rc);
7717 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0);
7718 if (rc != 0) {
7719 pr_err("error %d\n", rc);
7722 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0);
7723 if (rc != 0) {
7724 pr_err("error %d\n", rc);
7727 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0);
7728 if (rc != 0) {
7729 pr_err("error %d\n", rc);
7733 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7734 if (rc != 0) {
7735 pr_err("error %d\n", rc);
7738 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7739 if (rc != 0) {
7740 pr_err("error %d\n", rc);
7743 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7744 if (rc != 0) {
7745 pr_err("error %d\n", rc);
7748 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0);
7749 if (rc != 0) {
7750 pr_err("error %d\n", rc);
7753 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7754 if (rc != 0) {
7755 pr_err("error %d\n", rc);
7758 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7759 if (rc != 0) {
7760 pr_err("error %d\n", rc);
7763 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0);
7764 if (rc != 0) {
7765 pr_err("error %d\n", rc);
7768 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7769 if (rc != 0) {
7770 pr_err("error %d\n", rc);
7773 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7774 if (rc != 0) {
7775 pr_err("error %d\n", rc);
7778 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7779 if (rc != 0) {
7780 pr_err("error %d\n", rc);
7783 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7784 if (rc != 0) {
7785 pr_err("error %d\n", rc);
7788 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7789 if (rc != 0) {
7790 pr_err("error %d\n", rc);
7793 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7794 if (rc != 0) {
7795 pr_err("error %d\n", rc);
7798 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7799 if (rc != 0) {
7800 pr_err("error %d\n", rc);
7803 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7804 if (rc != 0) {
7805 pr_err("error %d\n", rc);
7808 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7809 if (rc != 0) {
7810 pr_err("error %d\n", rc);
7813 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0);
7814 if (rc != 0) {
7815 pr_err("error %d\n", rc);
7818 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7819 if (rc != 0) {
7820 pr_err("error %d\n", rc);
7823 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7824 if (rc != 0) {
7825 pr_err("error %d\n", rc);
7828 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7829 if (rc != 0) {
7830 pr_err("error %d\n", rc);
7834 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0);
7835 if (rc != 0) {
7836 pr_err("error %d\n", rc);
7842 return rc;
7864 int rc;
8068 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
8069 if (rc != 0) {
8070 pr_err("error %d\n", rc);
8073 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
8074 if (rc != 0) {
8075 pr_err("error %d\n", rc);
8078 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
8079 if (rc != 0) {
8080 pr_err("error %d\n", rc);
8083 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
8084 if (rc != 0) {
8085 pr_err("error %d\n", rc);
8088 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
8089 if (rc != 0) {
8090 pr_err("error %d\n", rc);
8093 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
8094 if (rc != 0) {
8095 pr_err("error %d\n", rc);
8098 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
8099 if (rc != 0) {
8100 pr_err("error %d\n", rc);
8110 rc = scu_command(dev_addr, &cmd_scu);
8111 if (rc != 0) {
8112 pr_err("error %d\n", rc);
8129 rc = scu_command(dev_addr, &cmd_scu);
8130 if (rc != 0) {
8131 pr_err("error %d\n", rc);
8141 rc = scu_command(dev_addr, &cmd_scu);
8142 if (rc != 0) {
8143 pr_err("error %d\n", rc);
8147 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0);
8148 if (rc != 0) {
8149 pr_err("error %d\n", rc);
8153 rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate);
8154 if (rc != 0) {
8155 pr_err("error %d\n", rc);
8164 rc = set_frequency(demod, channel, tuner_freq_offset);
8165 if (rc != 0) {
8166 pr_err("error %d\n", rc);
8173 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0);
8174 if (rc != 0) {
8175 pr_err("error %d\n", rc);
8178 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0);
8179 if (rc != 0) {
8180 pr_err("error %d\n", rc);
8187 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
8188 if (rc != 0) {
8189 pr_err("error %d\n", rc);
8193 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
8194 if (rc != 0) {
8195 pr_err("error %d\n", rc);
8198 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
8199 if (rc != 0) {
8200 pr_err("error %d\n", rc);
8203 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0);
8204 if (rc != 0) {
8205 pr_err("error %d\n", rc);
8209 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0);
8210 if (rc != 0) {
8211 pr_err("error %d\n", rc);
8215 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0);
8216 if (rc != 0) {
8217 pr_err("error %d\n", rc);
8220 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
8221 if (rc != 0) {
8222 pr_err("error %d\n", rc);
8225 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0);
8226 if (rc != 0) {
8227 pr_err("error %d\n", rc);
8230 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
8231 if (rc != 0) {
8232 pr_err("error %d\n", rc);
8235 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0);
8236 if (rc != 0) {
8237 pr_err("error %d\n", rc);
8240 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0);
8241 if (rc != 0) {
8242 pr_err("error %d\n", rc);
8245 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0);
8246 if (rc != 0) {
8247 pr_err("error %d\n", rc);
8251 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
8252 if (rc != 0) {
8253 pr_err("error %d\n", rc);
8256 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0);
8257 if (rc != 0) {
8258 pr_err("error %d\n", rc);
8262 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0);
8263 if (rc != 0) {
8264 pr_err("error %d\n", rc);
8268 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0);
8269 if (rc != 0) {
8270 pr_err("error %d\n", rc);
8273 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0);
8274 if (rc != 0) {
8275 pr_err("error %d\n", rc);
8278 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8279 if (rc != 0) {
8280 pr_err("error %d\n", rc);
8288 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8289 if (rc != 0) {
8290 pr_err("error %d\n", rc);
8293 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0);
8294 if (rc != 0) {
8295 pr_err("error %d\n", rc);
8298 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8299 if (rc != 0) {
8300 pr_err("error %d\n", rc);
8306 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8307 if (rc != 0) {
8308 pr_err("error %d\n", rc);
8311 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0);
8312 if (rc != 0) {
8313 pr_err("error %d\n", rc);
8316 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0);
8317 if (rc != 0) {
8318 pr_err("error %d\n", rc);
8327 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0);
8328 if (rc != 0) {
8329 pr_err("error %d\n", rc);
8332 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0);
8333 if (rc != 0) {
8334 pr_err("error %d\n", rc);
8337 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0);
8338 if (rc != 0) {
8339 pr_err("error %d\n", rc);
8342 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0);
8343 if (rc != 0) {
8344 pr_err("error %d\n", rc);
8347 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0);
8348 if (rc != 0) {
8349 pr_err("error %d\n", rc);
8352 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0);
8353 if (rc != 0) {
8354 pr_err("error %d\n", rc);
8357 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0);
8358 if (rc != 0) {
8359 pr_err("error %d\n", rc);
8362 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0);
8363 if (rc != 0) {
8364 pr_err("error %d\n", rc);
8367 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0);
8368 if (rc != 0) {
8369 pr_err("error %d\n", rc);
8372 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0);
8373 if (rc != 0) {
8374 pr_err("error %d\n", rc);
8377 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0);
8378 if (rc != 0) {
8379 pr_err("error %d\n", rc);
8382 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0);
8383 if (rc != 0) {
8384 pr_err("error %d\n", rc);
8387 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0);
8388 if (rc != 0) {
8389 pr_err("error %d\n", rc);
8392 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0);
8393 if (rc != 0) {
8394 pr_err("error %d\n", rc);
8397 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0);
8398 if (rc != 0) {
8399 pr_err("error %d\n", rc);
8402 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0);
8403 if (rc != 0) {
8404 pr_err("error %d\n", rc);
8407 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0);
8408 if (rc != 0) {
8409 pr_err("error %d\n", rc);
8412 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0);
8413 if (rc != 0) {
8414 pr_err("error %d\n", rc);
8417 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0);
8418 if (rc != 0) {
8419 pr_err("error %d\n", rc);
8422 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0);
8423 if (rc != 0) {
8424 pr_err("error %d\n", rc);
8428 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0);
8429 if (rc != 0) {
8430 pr_err("error %d\n", rc);
8433 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0);
8434 if (rc != 0) {
8435 pr_err("error %d\n", rc);
8438 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0);
8439 if (rc != 0) {
8440 pr_err("error %d\n", rc);
8443 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0);
8444 if (rc != 0) {
8445 pr_err("error %d\n", rc);
8448 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
8449 if (rc != 0) {
8450 pr_err("error %d\n", rc);
8457 rc = set_iqm_af(demod, true);
8458 if (rc != 0) {
8459 pr_err("error %d\n", rc);
8462 rc = adc_synchronization(demod);
8463 if (rc != 0) {
8464 pr_err("error %d\n", rc);
8468 rc = init_agc(demod);
8469 if (rc != 0) {
8470 pr_err("error %d\n", rc);
8473 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false);
8474 if (rc != 0) {
8475 pr_err("error %d\n", rc);
8478 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false);
8479 if (rc != 0) {
8480 pr_err("error %d\n", rc);
8489 rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg);
8490 if (rc != 0) {
8491 pr_err("error %d\n", rc);
8495 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg));
8496 if (rc != 0) {
8497 pr_err("error %d\n", rc);
8504 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8505 if (rc != 0) {
8506 pr_err("error %d\n", rc);
8509 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8510 if (rc != 0) {
8511 pr_err("error %d\n", rc);
8517 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8518 if (rc != 0) {
8519 pr_err("error %d\n", rc);
8522 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8523 if (rc != 0) {
8524 pr_err("error %d\n", rc);
8529 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8530 if (rc != 0) {
8531 pr_err("error %d\n", rc);
8534 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8535 if (rc != 0) {
8536 pr_err("error %d\n", rc);
8544 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8545 if (rc != 0) {
8546 pr_err("error %d\n", rc);
8549 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8550 if (rc != 0) {
8551 pr_err("error %d\n", rc);
8559 rc = set_qam16(demod);
8560 if (rc != 0) {
8561 pr_err("error %d\n", rc);
8566 rc = set_qam32(demod);
8567 if (rc != 0) {
8568 pr_err("error %d\n", rc);
8573 rc = set_qam64(demod);
8574 if (rc != 0) {
8575 pr_err("error %d\n", rc);
8580 rc = set_qam128(demod);
8581 if (rc != 0) {
8582 pr_err("error %d\n", rc);
8587 rc = set_qam256(demod);
8588 if (rc != 0) {
8589 pr_err("error %d\n", rc);
8599 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
8600 if (rc != 0) {
8601 pr_err("error %d\n", rc);
8606 rc = set_mpegtei_handling(demod);
8607 if (rc != 0) {
8608 pr_err("error %d\n", rc);
8611 rc = bit_reverse_mpeg_output(demod);
8612 if (rc != 0) {
8613 pr_err("error %d\n", rc);
8616 rc = set_mpeg_start_width(demod);
8617 if (rc != 0) {
8618 pr_err("error %d\n", rc);
8629 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
8630 if (rc != 0) {
8631 pr_err("error %d\n", rc);
8646 rc = scu_command(dev_addr, &cmd_scu);
8647 if (rc != 0) {
8648 pr_err("error %d\n", rc);
8653 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
8654 if (rc != 0) {
8655 pr_err("error %d\n", rc);
8658 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0);
8659 if (rc != 0) {
8660 pr_err("error %d\n", rc);
8663 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
8664 if (rc != 0) {
8665 pr_err("error %d\n", rc);
8671 return rc;
8681 int rc;
8692 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0);
8693 if (rc != 0) {
8694 pr_err("error %d\n", rc);
8697 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0);
8698 if (rc != 0) {
8699 pr_err("error %d\n", rc);
8704 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0);
8705 if (rc != 0) {
8706 pr_err("error %d\n", rc);
8709 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0);
8710 if (rc != 0) {
8711 pr_err("error %d\n", rc);
8715 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0);
8716 if (rc != 0) {
8717 pr_err("error %d\n", rc);
8720 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0);
8721 if (rc != 0) {
8722 pr_err("error %d\n", rc);
8730 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8731 if (rc != 0) {
8732 pr_err("error %d\n", rc);
8736 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8737 if (rc != 0) {
8738 pr_err("error %d\n", rc);
8741 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8742 if (rc != 0) {
8743 pr_err("error %d\n", rc);
8748 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0);
8749 if (rc != 0) {
8750 pr_err("error %d\n", rc);
8753 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0);
8754 if (rc != 0) {
8755 pr_err("error %d\n", rc);
8758 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0);
8759 if (rc != 0) {
8760 pr_err("error %d\n", rc);
8765 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
8766 if (rc != 0) {
8767 pr_err("error %d\n", rc);
8774 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8775 if (rc != 0) {
8776 pr_err("error %d\n", rc);
8781 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8782 if (rc != 0) {
8783 pr_err("error %d\n", rc);
8786 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8787 if (rc != 0) {
8788 pr_err("error %d\n", rc);
8793 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8794 if (rc != 0) {
8795 pr_err("error %d\n", rc);
8798 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8799 if (rc != 0) {
8800 pr_err("error %d\n", rc);
8806 rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8807 if (rc != 0) {
8808 pr_err("error %d\n", rc);
8811 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8812 if (rc != 0) {
8813 pr_err("error %d\n", rc);
8819 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8820 if (rc != 0) {
8821 pr_err("error %d\n", rc);
8824 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8825 if (rc != 0) {
8826 pr_err("error %d\n", rc);
8830 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0);
8831 if (rc != 0) {
8832 pr_err("error %d\n", rc);
8838 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0);
8839 if (rc != 0) {
8840 pr_err("error %d\n", rc);
8844 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0);
8845 if (rc != 0) {
8846 pr_err("error %d\n", rc);
8852 return rc;
8878 int rc;
8890 rc = ctrl_lock_status(demod, lock_status);
8891 if (rc != 0) {
8892 pr_err("error %d\n", rc);
8899 rc = ctrl_get_qam_sig_quality(demod);
8900 if (rc != 0) {
8901 pr_err("error %d\n", rc);
8916 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8917 if (rc != 0) {
8918 pr_err("error %d\n", rc);
8921 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8922 if (rc != 0) {
8923 pr_err("error %d\n", rc);
8934 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8935 if (rc != 0) {
8936 pr_err("error %d\n", rc);
8939 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0);
8940 if (rc != 0) {
8941 pr_err("error %d\n", rc);
8946 rc = qam_flip_spec(demod, channel);
8947 if (rc != 0) {
8948 pr_err("error %d\n", rc);
8968 rc = ctrl_get_qam_sig_quality(demod);
8969 if (rc != 0) {
8970 pr_err("error %d\n", rc);
8974 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8975 if (rc != 0) {
8976 pr_err("error %d\n", rc);
8979 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8980 if (rc != 0) {
8981 pr_err("error %d\n", rc);
9005 return rc;
9026 int rc;
9037 rc = ctrl_lock_status(demod, lock_status);
9038 if (rc != 0) {
9039 pr_err("error %d\n", rc);
9045 rc = ctrl_get_qam_sig_quality(demod);
9046 if (rc != 0) {
9047 pr_err("error %d\n", rc);
9063 rc = qam_flip_spec(demod, channel);
9064 if (rc != 0) {
9065 pr_err("error %d\n", rc);
9089 return rc;
9104 int rc;
9128 rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL);
9129 if (rc != 0) {
9130 pr_err("error %d\n", rc);
9135 rc = qam64auto(demod, channel, tuner_freq_offset,
9138 rc = qam256auto(demod, channel, tuner_freq_offset,
9140 if (rc != 0) {
9141 pr_err("error %d\n", rc);
9158 rc = set_qam(demod, channel, tuner_freq_offset,
9160 if (rc != 0) {
9161 pr_err("error %d\n", rc);
9164 rc = qam256auto(demod, channel, tuner_freq_offset,
9166 if (rc != 0) {
9167 pr_err("error %d\n", rc);
9184 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9187 if (rc != 0) {
9188 pr_err("error %d\n", rc);
9191 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9194 if (rc != 0) {
9195 pr_err("error %d\n", rc);
9198 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9201 if (rc != 0) {
9202 pr_err("error %d\n", rc);
9206 rc = set_qam(demod, channel, tuner_freq_offset,
9208 if (rc != 0) {
9209 pr_err("error %d\n", rc);
9212 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9215 if (rc != 0) {
9216 pr_err("error %d\n", rc);
9220 rc = qam64auto(demod, channel, tuner_freq_offset,
9222 if (rc != 0) {
9223 pr_err("error %d\n", rc);
9239 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9242 if (rc != 0) {
9243 pr_err("error %d\n", rc);
9246 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9249 if (rc != 0) {
9250 pr_err("error %d\n", rc);
9253 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9256 if (rc != 0) {
9257 pr_err("error %d\n", rc);
9261 rc = set_qam(demod, channel, tuner_freq_offset,
9263 if (rc != 0) {
9264 pr_err("error %d\n", rc);
9267 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9270 if (rc != 0) {
9271 pr_err("error %d\n", rc);
9274 rc = qam64auto(demod, channel, tuner_freq_offset,
9276 if (rc != 0) {
9277 pr_err("error %d\n", rc);
9294 return rc;
9311 int rc;
9323 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0);
9324 if (rc != 0) {
9325 pr_err("error %d\n", rc);
9329 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0);
9330 if (rc != 0) {
9331 pr_err("error %d\n", rc);
9335 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0);
9336 if (rc != 0) {
9337 pr_err("error %d\n", rc);
9341 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0);
9342 if (rc != 0) {
9343 pr_err("error %d\n", rc);
9347 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0);
9348 if (rc != 0) {
9349 pr_err("error %d\n", rc);
9365 return rc;
9388 int rc;
9396 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0);
9397 if (rc != 0) {
9398 pr_err("error %d\n", rc);
9402 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0);
9403 if (rc != 0) {
9404 pr_err("error %d\n", rc);
9447 return rc;
9471 int rc;
9501 rc = get_qamrs_err_count(dev_addr, &measuredrs_errors);
9502 if (rc != 0) {
9503 pr_err("error %d\n", rc);
9507 rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0);
9508 if (rc != 0) {
9509 pr_err("error %d\n", rc);
9513 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0);
9514 if (rc != 0) {
9515 pr_err("error %d\n", rc);
9566 rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0);
9567 if (rc != 0) {
9568 pr_err("error %d\n", rc);
9649 rc = get_acc_pkt_err(demod, &sig_quality->packet_error);
9650 if (rc != 0) {
9651 pr_err("error %d\n", rc);
9665 return rc;
9757 int rc;
9769 rc = scu_command(dev_addr, &cmd_scu);
9770 if (rc != 0) {
9771 pr_err("error %d\n", rc);
9775 rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0);
9776 if (rc != 0) {
9777 pr_err("error %d\n", rc);
9781 rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0);
9782 if (rc != 0) {
9783 pr_err("error %d\n", rc);
9787 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
9788 if (rc != 0) {
9789 pr_err("error %d\n", rc);
9792 rc = set_iqm_af(demod, false);
9793 if (rc != 0) {
9794 pr_err("error %d\n", rc);
9798 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
9799 if (rc != 0) {
9800 pr_err("error %d\n", rc);
9803 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
9804 if (rc != 0) {
9805 pr_err("error %d\n", rc);
9808 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
9809 if (rc != 0) {
9810 pr_err("error %d\n", rc);
9813 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
9814 if (rc != 0) {
9815 pr_err("error %d\n", rc);
9818 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
9819 if (rc != 0) {
9820 pr_err("error %d\n", rc);
9824 rc = power_down_aud(demod);
9825 if (rc != 0) {
9826 pr_err("error %d\n", rc);
9832 return rc;
9847 int rc;
9852 rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0);
9853 if (rc != 0) {
9854 pr_err("error %d\n", rc);
9862 return rc;
9875 int rc;
9879 rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0);
9880 if (rc != 0) {
9881 pr_err("error %d\n", rc);
9888 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0);
9889 if (rc != 0) {
9890 pr_err("error %d\n", rc);
9896 return rc;
9925 int rc;
9962 rc = scu_command(dev_addr, &scu_cmd);
9963 if (rc != 0) {
9964 pr_err("error %d\n", rc);
9967 rc = set_orx_nsu_aox(demod, false);
9968 if (rc != 0) {
9969 pr_err("error %d\n", rc);
9972 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
9973 if (rc != 0) {
9974 pr_err("error %d\n", rc);
10004 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
10005 if (rc != 0) {
10006 pr_err("error %d\n", rc);
10014 rc = scu_command(dev_addr, &scu_cmd);
10015 if (rc != 0) {
10016 pr_err("error %d\n", rc);
10027 rc = scu_command(dev_addr, &scu_cmd);
10028 if (rc != 0) {
10029 pr_err("error %d\n", rc);
10103 rc = scu_command(dev_addr, &scu_cmd);
10104 if (rc != 0) {
10105 pr_err("error %d\n", rc);
10109 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
10110 if (rc != 0) {
10111 pr_err("error %d\n", rc);
10114 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0);
10115 if (rc != 0) {
10116 pr_err("error %d\n", rc);
10119 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0);
10120 if (rc != 0) {
10121 pr_err("error %d\n", rc);
10124 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
10125 if (rc != 0) {
10126 pr_err("error %d\n", rc);
10130 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0);
10131 if (rc != 0) {
10132 pr_err("error %d\n", rc);
10135 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0);
10136 if (rc != 0) {
10137 pr_err("error %d\n", rc);
10140 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0);
10141 if (rc != 0) {
10142 pr_err("error %d\n", rc);
10147 rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0);
10148 if (rc != 0) {
10149 pr_err("error %d\n", rc);
10154 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0);
10155 if (rc != 0) {
10156 pr_err("error %d\n", rc);
10161 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0);
10162 if (rc != 0) {
10163 pr_err("error %d\n", rc);
10166 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0);
10167 if (rc != 0) {
10168 pr_err("error %d\n", rc);
10173 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0);
10174 if (rc != 0) {
10175 pr_err("error %d\n", rc);
10178 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0);
10179 if (rc != 0) {
10180 pr_err("error %d\n", rc);
10183 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0);
10184 if (rc != 0) {
10185 pr_err("error %d\n", rc);
10188 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0);
10189 if (rc != 0) {
10190 pr_err("error %d\n", rc);
10195 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0);
10196 if (rc != 0) {
10197 pr_err("error %d\n", rc);
10200 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0);
10201 if (rc != 0) {
10202 pr_err("error %d\n", rc);
10205 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0);
10206 if (rc != 0) {
10207 pr_err("error %d\n", rc);
10210 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0);
10211 if (rc != 0) {
10212 pr_err("error %d\n", rc);
10215 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0);
10216 if (rc != 0) {
10217 pr_err("error %d\n", rc);
10222 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0);
10223 if (rc != 0) {
10224 pr_err("error %d\n", rc);
10227 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0);
10228 if (rc != 0) {
10229 pr_err("error %d\n", rc);
10232 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0);
10233 if (rc != 0) {
10234 pr_err("error %d\n", rc);
10237 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0);
10238 if (rc != 0) {
10239 pr_err("error %d\n", rc);
10242 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0);
10243 if (rc != 0) {
10244 pr_err("error %d\n", rc);
10249 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0);
10250 if (rc != 0) {
10251 pr_err("error %d\n", rc);
10254 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0);
10255 if (rc != 0) {
10256 pr_err("error %d\n", rc);
10259 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0);
10260 if (rc != 0) {
10261 pr_err("error %d\n", rc);
10264 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0);
10265 if (rc != 0) {
10266 pr_err("error %d\n", rc);
10269 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0);
10270 if (rc != 0) {
10271 pr_err("error %d\n", rc);
10276 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0);
10277 if (rc != 0) {
10278 pr_err("error %d\n", rc);
10281 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0);
10282 if (rc != 0) {
10283 pr_err("error %d\n", rc);
10286 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0);
10287 if (rc != 0) {
10288 pr_err("error %d\n", rc);
10291 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0);
10292 if (rc != 0) {
10293 pr_err("error %d\n", rc);
10296 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0);
10297 if (rc != 0) {
10298 pr_err("error %d\n", rc);
10303 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0);
10304 if (rc != 0) {
10305 pr_err("error %d\n", rc);
10308 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0);
10309 if (rc != 0) {
10310 pr_err("error %d\n", rc);
10313 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0);
10314 if (rc != 0) {
10315 pr_err("error %d\n", rc);
10318 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0);
10319 if (rc != 0) {
10320 pr_err("error %d\n", rc);
10323 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0);
10324 if (rc != 0) {
10325 pr_err("error %d\n", rc);
10330 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0);
10331 if (rc != 0) {
10332 pr_err("error %d\n", rc);
10335 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0);
10336 if (rc != 0) {
10337 pr_err("error %d\n", rc);
10340 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0);
10341 if (rc != 0) {
10342 pr_err("error %d\n", rc);
10345 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0);
10346 if (rc != 0) {
10347 pr_err("error %d\n", rc);
10350 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0);
10351 if (rc != 0) {
10352 pr_err("error %d\n", rc);
10357 rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0);
10358 if (rc != 0) {
10359 pr_err("error %d\n", rc);
10362 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0);
10363 if (rc != 0) {
10364 pr_err("error %d\n", rc);
10370 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0);
10371 if (rc != 0) {
10372 pr_err("error %d\n", rc);
10375 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0);
10376 if (rc != 0) {
10377 pr_err("error %d\n", rc);
10381 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0);
10382 if (rc != 0) {
10383 pr_err("error %d\n", rc);
10386 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0);
10387 if (rc != 0) {
10388 pr_err("error %d\n", rc);
10399 rc = scu_command(dev_addr, &scu_cmd);
10400 if (rc != 0) {
10401 pr_err("error %d\n", rc);
10405 rc = set_orx_nsu_aox(demod, true);
10406 if (rc != 0) {
10407 pr_err("error %d\n", rc);
10410 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0);
10411 if (rc != 0) {
10412 pr_err("error %d\n", rc);
10420 return rc;
10448 int rc;
10511 rc = ctrl_set_uio_cfg(demod, &uio_cfg);
10512 if (rc != 0) {
10513 pr_err("error %d\n", rc);
10606 rc = ctrl_uio_write(demod, &uio1);
10607 if (rc != 0) {
10608 pr_err("error %d\n", rc);
10613 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
10614 if (rc != 0) {
10615 pr_err("error %d\n", rc);
10628 rc = set_vsb(demod);
10629 if (rc != 0) {
10630 pr_err("error %d\n", rc);
10633 rc = set_frequency(demod, channel, tuner_freq_offset);
10634 if (rc != 0) {
10635 pr_err("error %d\n", rc);
10643 rc = set_qam_channel(demod, channel, tuner_freq_offset);
10644 if (rc != 0) {
10645 pr_err("error %d\n", rc);
10660 return rc;
10687 int rc;
10691 rc = get_sig_strength(demod, &strength);
10692 if (rc < 0) {
10693 pr_err("error getting signal strength %d\n", rc);
10703 rc = get_acc_pkt_err(demod, &pkt);
10704 if (rc != 0) {
10705 pr_err("error %d\n", rc);
10718 rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt);
10719 if (rc != 0) {
10720 pr_err("error %d getting UCB\n", rc);
10730 rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt);
10731 if (rc != 0) {
10732 pr_err("error %d getting pre-ber\n", rc);
10741 rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt);
10742 if (rc != 0) {
10743 pr_err("error %d getting post-ber\n", rc);
10751 rc = get_vsbmer(dev_addr, &mer);
10752 if (rc != 0) {
10753 pr_err("error %d getting MER\n", rc);
10765 rc = ctrl_get_qam_sig_quality(demod);
10766 if (rc != 0) {
10767 pr_err("error %d\n", rc);
10778 return rc;
10803 int rc;
10842 rc = scu_command(dev_addr, &cmd_scu);
10843 if (rc != 0) {
10844 pr_err("error %d\n", rc);
10866 return rc;
10885 int rc;
10903 rc = power_down_qam(demod, false);
10904 if (rc != 0) {
10905 pr_err("error %d\n", rc);
10911 rc = power_down_vsb(demod, false);
10912 if (rc != 0) {
10913 pr_err("error %d\n", rc);
10938 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0);
10939 if (rc != 0) {
10940 pr_err("error %d\n", rc);
10947 rc = set_vsb_leak_n_gain(demod);
10948 if (rc != 0) {
10949 pr_err("error %d\n", rc);
10963 return rc;
11045 int rc;
11082 rc = power_up_device(demod);
11083 if (rc != 0) {
11084 pr_err("error %d\n", rc);
11110 rc = power_down_qam(demod, true);
11111 if (rc != 0) {
11112 pr_err("error %d\n", rc);
11117 rc = power_down_vsb(demod, true);
11118 if (rc != 0) {
11119 pr_err("error %d\n", rc);
11130 rc = power_down_atv(demod, ext_attr->standard, true);
11131 if (rc != 0) {
11132 pr_err("error %d\n", rc);
11147 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0);
11148 if (rc != 0) {
11149 pr_err("error %d\n", rc);
11152 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11153 if (rc != 0) {
11154 pr_err("error %d\n", rc);
11160 rc = init_hi(demod);
11161 if (rc != 0) {
11162 pr_err("error %d\n", rc);
11167 rc = hi_cfg_command(demod);
11168 if (rc != 0) {
11169 pr_err("error %d\n", rc);
11179 return rc;
11202 int rc;
11219 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0);
11220 if (rc != 0) {
11221 pr_err("error %d\n", rc);
11244 return rc;
11265 int rc;
11300 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0);
11301 if (rc != 0) {
11302 pr_err("error %d\n", rc);
11325 return rc;
11358 int rc;
11377 rc = ctrl_power_mode(demod, &power_mode);
11378 if (rc != 0) {
11379 pr_err("error %d\n", rc);
11383 rc = -EINVAL;
11389 rc = get_device_capabilities(demod);
11390 if (rc != 0) {
11391 pr_err("error %d\n", rc);
11403 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0);
11404 if (rc != 0) {
11405 pr_err("error %d\n", rc);
11408 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11409 if (rc != 0) {
11410 pr_err("error %d\n", rc);
11417 rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0);
11418 if (rc != 0) {
11419 pr_err("error %d\n", rc);
11423 rc = set_iqm_af(demod, false);
11424 if (rc != 0) {
11425 pr_err("error %d\n", rc);
11428 rc = set_orx_nsu_aox(demod, false);
11429 if (rc != 0) {
11430 pr_err("error %d\n", rc);
11434 rc = init_hi(demod);
11435 if (rc != 0) {
11436 pr_err("error %d\n", rc);
11444 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
11445 if (rc != 0) {
11446 pr_err("error %d\n", rc);
11450 rc = power_down_aud(demod);
11451 if (rc != 0) {
11452 pr_err("error %d\n", rc);
11456 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0);
11457 if (rc != 0) {
11458 pr_err("error %d\n", rc);
11474 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD);
11475 if (rc != 0) {
11476 pr_err("error %d while uploading the firmware\n", rc);
11480 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY);
11481 if (rc != 0) {
11483 rc);
11491 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11492 if (rc != 0) {
11493 pr_err("error %d\n", rc);
11504 rc = smart_ant_init(demod);
11505 if (rc != 0) {
11506 pr_err("error %d\n", rc);
11529 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0);
11530 if (rc != 0) {
11531 pr_err("error %d\n", rc);
11534 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0);
11535 if (rc != 0) {
11536 pr_err("error %d\n", rc);
11540 rc = ctrl_set_oob(demod, NULL);
11541 if (rc != 0) {
11542 pr_err("error %d\n", rc);
11554 return rc;
11567 int rc;
11578 rc = ctrl_power_mode(demod, &power_mode);
11579 if (rc != 0) {
11580 pr_err("error %d\n", rc);
11584 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11585 if (rc != 0) {
11586 pr_err("error %d\n", rc);
11590 rc = ctrl_power_mode(demod, &power_mode);
11591 if (rc != 0) {
11592 pr_err("error %d\n", rc);
11602 return rc;
11747 int rc;
11765 rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent);
11766 if (rc < 0) {
11768 return rc;
11773 rc = -EINVAL;
11793 rc = -EINVAL;
11799 rc = drx_check_firmware(demod, (u8 *)mc_data_init, size);
11800 if (rc)
11835 rc = -EINVAL;
11852 rc = -EIO;
11911 return rc;
12226 int rc = 0;
12231 rc = drxj_open(demod);
12232 if (rc != 0)
12233 pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc);
12237 return rc;