Lines Matching defs:d9
99 } d9;
1005 dib9000_write_word(state, 911, state->chip.d9.cfg.if_drives);
1085 if (dib9000_fw_boot(state, NULL, 0, state->chip.d9.cfg.microcode_B_fe_buffer, state->chip.d9.cfg.microcode_B_fe_size) != 0)
1089 for (i = 0; i < ARRAY_SIZE(state->chip.d9.cfg.gpio_function); i++) {
1090 f = &state->chip.d9.cfg.gpio_function[i];
1110 b[0] = state->chip.d9.cfg.subband.size; /* type == 0 -> GPIO - PWM not yet supported */
1111 for (i = 0; i < state->chip.d9.cfg.subband.size; i++) {
1112 b[1 + i * 4] = state->chip.d9.cfg.subband.subband[i].f_mhz;
1113 b[2 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.mask;
1114 b[3 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.direction;
1115 b[4 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.value;
1125 b[2] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000) >> 16) & 0xffff);
1126 b[3] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000)) & 0xffff);
1127 b[4] = (u16) ((state->chip.d9.cfg.vcxo_timer >> 16) & 0xffff);
1128 b[5] = (u16) ((state->chip.d9.cfg.vcxo_timer) & 0xffff);
1129 b[6] = (u16) ((state->chip.d9.cfg.timing_frequency >> 16) & 0xffff);
1130 b[7] = (u16) ((state->chip.d9.cfg.timing_frequency) & 0xffff);
1131 b[29] = state->chip.d9.cfg.if_drives;
1575 if (state->chip.d9.cfg.output_mpeg2_in_188_bytes)
2130 dib9000_fw_set_output_mode(state->fe[0], state->chip.d9.cfg.output_mode);
2486 memcpy(&st->chip.d9.cfg, cfg, sizeof(struct dib9000_config));
2512 if ((st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
2513 st->chip.d9.cfg.output_mode = OUTMODE_MPEG2_FIFO;