Lines Matching refs:state
171 static u16 __dib8000_read_word(struct dib8000_state *state, u16 reg)
175 state->i2c_write_buffer[0] = reg >> 8;
176 state->i2c_write_buffer[1] = reg & 0xff;
178 memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
179 state->msg[0].addr = state->i2c.addr >> 1;
180 state->msg[0].flags = 0;
181 state->msg[0].buf = state->i2c_write_buffer;
182 state->msg[0].len = 2;
183 state->msg[1].addr = state->i2c.addr >> 1;
184 state->msg[1].flags = I2C_M_RD;
185 state->msg[1].buf = state->i2c_read_buffer;
186 state->msg[1].len = 2;
188 if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2)
191 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
196 static u16 dib8000_read_word(struct dib8000_state *state, u16 reg)
200 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
205 ret = __dib8000_read_word(state, reg);
207 mutex_unlock(&state->i2c_buffer_lock);
212 static u32 dib8000_read32(struct dib8000_state *state, u16 reg)
216 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
221 rw[0] = __dib8000_read_word(state, reg + 0);
222 rw[1] = __dib8000_read_word(state, reg + 1);
224 mutex_unlock(&state->i2c_buffer_lock);
251 static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val)
255 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
260 state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
261 state->i2c_write_buffer[1] = reg & 0xff;
262 state->i2c_write_buffer[2] = (val >> 8) & 0xff;
263 state->i2c_write_buffer[3] = val & 0xff;
265 memset(&state->msg[0], 0, sizeof(struct i2c_msg));
266 state->msg[0].addr = state->i2c.addr >> 1;
267 state->msg[0].flags = 0;
268 state->msg[0].buf = state->i2c_write_buffer;
269 state->msg[0].len = 4;
271 ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ?
273 mutex_unlock(&state->i2c_buffer_lock);
379 static u16 fft_to_mode(struct dib8000_state *state)
382 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
398 static void dib8000_set_acquisition_mode(struct dib8000_state *state)
400 u16 nud = dib8000_read_word(state, 298);
403 dib8000_write_word(state, 298, nud);
407 struct dib8000_state *state = fe->demodulator_priv;
410 state->output_mode = mode;
413 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
416 &state->fe[0], mode);
429 if (state->cfg.hostbus_diversity) {
446 dib8000_set_acquisition_mode(state);
451 &state->fe[0]);
455 if (state->cfg.output_mpeg2_in_188_bytes)
458 dib8000_write_word(state, 299, smo_mode);
459 dib8000_write_word(state, 300, fifo_threshold); /* synchronous fread */
460 dib8000_write_word(state, 1286, outreg);
461 dib8000_write_word(state, 1291, sram);
468 struct dib8000_state *state = fe->demodulator_priv;
469 u16 tmp, sync_wait = dib8000_read_word(state, 273) & 0xfff0;
472 if (!state->differential_constellation) {
473 dib8000_write_word(state, 272, 1 << 9); //dvsy_off_lmod4 = 1
474 dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2); // sync_enable = 1; comb_mode = 2
476 dib8000_write_word(state, 272, 0); //dvsy_off_lmod4 = 0
477 dib8000_write_word(state, 273, sync_wait); // sync_enable = 0; comb_mode = 0
479 state->diversity_onoff = onoff;
483 dib8000_write_word(state, 270, 1);
484 dib8000_write_word(state, 271, 0);
487 dib8000_write_word(state, 270, 6);
488 dib8000_write_word(state, 271, 6);
491 dib8000_write_word(state, 270, 0);
492 dib8000_write_word(state, 271, 1);
496 if (state->revision == 0x8002) {
497 tmp = dib8000_read_word(state, 903);
498 dib8000_write_word(state, 903, tmp & ~(1 << 3));
500 dib8000_write_word(state, 903, tmp | (1 << 3));
505 static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode)
509 reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3,
512 if (state->revision != 0x8090)
513 reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
515 reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80;
525 if (state->revision != 0x8090)
531 if (state->revision != 0x8090)
539 dib8000_write_word(state, 774, reg_774);
540 dib8000_write_word(state, 775, reg_775);
541 dib8000_write_word(state, 776, reg_776);
542 dib8000_write_word(state, 900, reg_900);
543 dib8000_write_word(state, 1280, reg_1280);
546 static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no)
549 u16 reg, reg_907 = dib8000_read_word(state, 907);
550 u16 reg_908 = dib8000_read_word(state, 908);
554 if (state->revision != 0x8090) {
556 ret |= dib8000_write_word(state, 908, reg_908);
559 reg = dib8000_read_word(state, 1925);
561 dib8000_write_word(state, 1925, reg |
565 reg = dib8000_read_word(state, 1925);
568 dib8000_write_word(state, 1925, reg & ~(1<<4));
570 reg = dib8000_read_word(state, 921) & ~((0x3 << 14)
574 dib8000_write_word(state, 921, reg | (1 << 14)
580 if (state->revision == 0x8090) {
581 reg = dib8000_read_word(state, 1925);
583 dib8000_write_word(state, 1925,
611 ret |= dib8000_write_word(state, 907, reg_907);
612 ret |= dib8000_write_word(state, 908, reg_908);
619 struct dib8000_state *state = fe->demodulator_priv;
625 if (state->timf == 0) {
627 timf = state->timf_default;
630 timf = state->timf;
633 dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff));
634 dib8000_write_word(state, 30, (u16) ((timf) & 0xffff));
639 static int dib8000_sad_calib(struct dib8000_state *state)
643 if (state->revision == 0x8090) {
644 dib8000_write_word(state, 922, (sad_sel << 2));
645 dib8000_write_word(state, 923, 2048);
647 dib8000_write_word(state, 922, (sad_sel << 2) | 0x1);
648 dib8000_write_word(state, 922, (sad_sel << 2));
651 dib8000_write_word(state, 923, (0 << 1) | (0 << 0));
652 dib8000_write_word(state, 924, 776);
655 dib8000_write_word(state, 923, (1 << 0));
656 dib8000_write_word(state, 923, (0 << 0));
665 struct dib8000_state *state = fe->demodulator_priv;
668 state->wbd_ref = value;
669 return dib8000_write_word(state, 106, value);
672 static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_config *bw)
675 if (state->revision != 0x8090) {
676 dib8000_write_word(state, 23,
678 dib8000_write_word(state, 24,
681 dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff));
682 dib8000_write_word(state, 24,
685 dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff));
686 dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff));
687 dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003));
689 if (state->revision != 0x8090)
690 dib8000_write_word(state, 922, bw->sad_cfg);
693 static void dib8000_reset_pll(struct dib8000_state *state)
695 const struct dibx000_bandwidth_config *pll = state->cfg.pll;
698 if (state->revision != 0x8090) {
699 dib8000_write_word(state, 901,
707 dib8000_write_word(state, 902, clk_cfg1);
709 dib8000_write_word(state, 902, clk_cfg1);
714 if (state->cfg.pll->ADClkSrc == 0)
715 dib8000_write_word(state, 904,
719 else if (state->cfg.refclksel != 0)
720 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
721 ((state->cfg.refclksel & 0x3) << 10) |
725 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
729 dib8000_write_word(state, 1856, (!pll->pll_reset<<13) |
733 reg = dib8000_read_word(state, 1857);
734 dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15));
736 reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */
737 dib8000_write_word(state, 1858, reg | 1);
739 dib8000_write_word(state, 904, (pll->modulo << 8));
742 dib8000_reset_pll_common(state, pll);
748 struct dib8000_state *state = fe->demodulator_priv;
749 u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856);
750 u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ;
762 if (state->revision == 0x8090) {
764 reg_1857 = dib8000_read_word(state, 1857);
766 dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15));
768 dib8000_write_word(state, 1856, reg_1856 |
773 internal = dib8000_read32(state, 23) / 1000;
780 dib8000_write_word(state, 23,
782 dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff));
784 dib8000_write_word(state, 1857, reg_1857 | (1 << 15));
786 while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1)
790 reg_1856 = dib8000_read_word(state, 1856);
794 if (bw != state->current_demod_bw) {
796 dprintk("PLL: Bandwidth Change %d MHz -> %d MHz (prediv: %d->%d)\n", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv);
798 if (state->cfg.pll->pll_prediv != oldprediv) {
802 dprintk("PLL: New Setting for %d MHz Bandwidth (prediv: %d, ratio: %d)\n", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_ratio);
803 dib8000_write_word(state, 902, dib8000_read_word(state, 902) | (1<<3)); /* bypass PLL */
804 dib8000_reset_pll(state);
805 dib8000_write_word(state, 898, 0x0004); /* sad */
807 ratio = state->cfg.pll->pll_ratio;
809 state->current_demod_bw = bw;
814 dprintk("PLL: Update ratio (prediv: %d, ratio: %d)\n", state->cfg.pll->pll_prediv, ratio);
815 dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL ratio is updated. */
855 struct dib8000_state *state = fe->demodulator_priv;
856 return dib8000_cfg_gpio(state, num, dir, val);
997 struct dib8000_state *state = fe->demodulator_priv;
998 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
1025 state->init_ucb = -ucb;
1026 state->ber_jiffies_stats = 0;
1027 state->per_jiffies_stats = 0;
1028 memset(&state->ber_jiffies_stats_layer, 0,
1029 sizeof(state->ber_jiffies_stats_layer));
1034 struct dib8000_state *state = fe->demodulator_priv;
1036 if ((state->revision = dib8000_identify(&state->i2c)) == 0)
1040 if (state->revision != 0x8090)
1041 dib8000_write_word(state, 1287, 0x0003);
1043 if (state->revision == 0x8000)
1046 dibx000_reset_i2c_master(&state->i2c_master);
1048 dib8000_set_power_mode(state, DIB8000_POWER_ALL);
1051 dib8000_set_adc_state(state, DIBX000_ADC_OFF);
1054 dib8000_write_word(state, 770, 0xffff);
1055 dib8000_write_word(state, 771, 0xffff);
1056 dib8000_write_word(state, 772, 0xfffc);
1057 dib8000_write_word(state, 898, 0x000c); /* restart sad */
1058 if (state->revision == 0x8090)
1059 dib8000_write_word(state, 1280, 0x0045);
1061 dib8000_write_word(state, 1280, 0x004d);
1062 dib8000_write_word(state, 1281, 0x000c);
1064 dib8000_write_word(state, 770, 0x0000);
1065 dib8000_write_word(state, 771, 0x0000);
1066 dib8000_write_word(state, 772, 0x0000);
1067 dib8000_write_word(state, 898, 0x0004); // sad
1068 dib8000_write_word(state, 1280, 0x0000);
1069 dib8000_write_word(state, 1281, 0x0000);
1072 if (state->revision != 0x8090) {
1073 if (state->cfg.drives)
1074 dib8000_write_word(state, 906, state->cfg.drives);
1078 dib8000_write_word(state, 906, 0x2d98);
1082 dib8000_reset_pll(state);
1083 if (state->revision != 0x8090)
1084 dib8000_write_word(state, 898, 0x0004);
1086 if (dib8000_reset_gpio(state) != 0)
1089 if ((state->revision != 0x8090) &&
1093 state->current_agc = NULL;
1097 if (state->cfg.pll->ifreq == 0)
1098 dib8000_write_word(state, 40, 0x0755); /* P_iqc_corr_inh = 0 enable IQcorr block */
1100 dib8000_write_word(state, 40, 0x1f55); /* P_iqc_corr_inh = 1 disable IQcorr block */
1110 dib8000_write_word(state, r, *n++);
1117 state->isdbt_cfg_loaded = 0;
1120 if ((state->revision != 8090) && (state->cfg.div_cfg != 0))
1121 dib8000_write_word(state, 903, state->cfg.div_cfg);
1124 dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1));
1128 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON);
1129 dib8000_sad_calib(state);
1130 if (state->revision != 0x8090)
1131 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
1134 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5));
1136 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
1143 static void dib8000_restart_agc(struct dib8000_state *state)
1146 dib8000_write_word(state, 770, 0x0a00);
1147 dib8000_write_word(state, 770, 0x0000);
1150 static int dib8000_update_lna(struct dib8000_state *state)
1154 if (state->cfg.update_lna) {
1156 dyn_gain = dib8000_read_word(state, 390);
1158 if (state->cfg.update_lna(state->fe[0], dyn_gain)) {
1159 dib8000_restart_agc(state);
1166 static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)
1172 if (state->current_band == band && state->current_agc != NULL)
1174 state->current_band = band;
1176 for (i = 0; i < state->cfg.agc_config_count; i++)
1177 if (state->cfg.agc[i].band_caps & band) {
1178 agc = &state->cfg.agc[i];
1187 state->current_agc = agc;
1190 dib8000_write_word(state, 76, agc->setup);
1191 dib8000_write_word(state, 77, agc->inv_gain);
1192 dib8000_write_word(state, 78, agc->time_stabiliz);
1193 dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock);
1196 dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp);
1197 dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp);
1200 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
1203 if (state->wbd_ref != 0)
1204 dib8000_write_word(state, 106, state->wbd_ref);
1206 dib8000_write_word(state, 106, agc->wbd_ref);
1208 if (state->revision == 0x8090) {
1209 reg = dib8000_read_word(state, 922) & (0x3 << 2);
1210 dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2));
1213 dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
1214 dib8000_write_word(state, 108, agc->agc1_max);
1215 dib8000_write_word(state, 109, agc->agc1_min);
1216 dib8000_write_word(state, 110, agc->agc2_max);
1217 dib8000_write_word(state, 111, agc->agc2_min);
1218 dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
1219 dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
1220 dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
1221 dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
1223 dib8000_write_word(state, 75, agc->agc1_pt3);
1224 if (state->revision != 0x8090)
1225 dib8000_write_word(state, 923,
1226 (dib8000_read_word(state, 923) & 0xffe3) |
1234 struct dib8000_state *state = fe->demodulator_priv;
1235 dib8000_set_adc_state(state, DIBX000_ADC_ON);
1236 dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000)));
1239 static int dib8000_agc_soft_split(struct dib8000_state *state)
1243 if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0)
1247 agc = dib8000_read_word(state, 390);
1249 if (agc > state->current_agc->split.min_thres)
1250 split_offset = state->current_agc->split.min;
1251 else if (agc < state->current_agc->split.max_thres)
1252 split_offset = state->current_agc->split.max;
1254 split_offset = state->current_agc->split.max *
1255 (agc - state->current_agc->split.min_thres) /
1256 (state->current_agc->split.max_thres - state->current_agc->split.min_thres);
1261 dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset);
1267 struct dib8000_state *state = fe->demodulator_priv;
1268 enum frontend_tune_state *tune_state = &state->tune_state;
1277 if (state->revision != 0x8090)
1278 dib8000_set_adc_state(state, DIBX000_ADC_ON);
1280 dib8000_set_power_mode(state, DIB8000_POWER_ALL);
1282 reg = dib8000_read_word(state, 1947)&0xff00;
1283 dib8000_write_word(state, 1946,
1286 dib8000_write_word(state, 1947, reg | (1<<14) |
1290 reg = dib8000_read_word(state, 1920);
1291 dib8000_write_word(state, 1920, (reg | 0x3) &
1295 if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) {
1297 state->status = FE_STATUS_TUNE_FAILED;
1307 if (state->cfg.agc_control)
1308 state->cfg.agc_control(fe, 1);
1310 dib8000_restart_agc(state);
1321 if (dib8000_update_lna(state))
1329 dib8000_agc_soft_split(state);
1331 if (state->cfg.agc_control)
1332 state->cfg.agc_control(fe, 0);
1337 ret = dib8000_agc_soft_split(state);
1344 static void dib8096p_host_bus_drive(struct dib8000_state *state, u8 drive)
1351 reg = dib8000_read_word(state, 1798) &
1354 dib8000_write_word(state, 1798, reg);
1357 reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
1359 dib8000_write_word(state, 1799, reg);
1362 reg = dib8000_read_word(state, 1800) &
1365 dib8000_write_word(state, 1800, reg);
1368 reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
1370 dib8000_write_word(state, 1801, reg);
1373 reg = dib8000_read_word(state, 1802) &
1376 dib8000_write_word(state, 1802, reg);
1398 static void dib8096p_cfg_DibTx(struct dib8000_state *state, u32 P_Kin,
1404 dib8000_write_word(state, 1615, 1);
1405 dib8000_write_word(state, 1603, P_Kin);
1406 dib8000_write_word(state, 1605, P_Kout);
1407 dib8000_write_word(state, 1606, insertExtSynchro);
1408 dib8000_write_word(state, 1608, synchroMode);
1409 dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff);
1410 dib8000_write_word(state, 1610, syncWord & 0xffff);
1411 dib8000_write_word(state, 1612, syncSize);
1412 dib8000_write_word(state, 1615, 0);
1415 static void dib8096p_cfg_DibRx(struct dib8000_state *state, u32 P_Kin,
1426 dib8000_write_word(state, 1542, syncFreq);
1429 dib8000_write_word(state, 1554, 1);
1430 dib8000_write_word(state, 1536, P_Kin);
1431 dib8000_write_word(state, 1537, P_Kout);
1432 dib8000_write_word(state, 1539, synchroMode);
1433 dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff);
1434 dib8000_write_word(state, 1541, syncWord & 0xffff);
1435 dib8000_write_word(state, 1543, syncSize);
1436 dib8000_write_word(state, 1544, dataOutRate);
1437 dib8000_write_word(state, 1554, 0);
1440 static void dib8096p_enMpegMux(struct dib8000_state *state, int onoff)
1444 reg_1287 = dib8000_read_word(state, 1287);
1455 dib8000_write_word(state, 1287, reg_1287);
1458 static void dib8096p_configMpegMux(struct dib8000_state *state,
1465 dib8096p_enMpegMux(state, 0);
1468 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
1473 dib8000_write_word(state, 1287, reg_1287);
1475 dib8096p_enMpegMux(state, 1);
1478 static void dib8096p_setDibTxMux(struct dib8000_state *state, int mode)
1480 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7);
1485 dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
1489 dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
1493 dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
1498 dib8000_write_word(state, 1288, reg_1288);
1501 static void dib8096p_setHostBusMux(struct dib8000_state *state, int mode)
1503 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4);
1508 dib8096p_enMpegMux(state, 0);
1513 dib8096p_enMpegMux(state, 0);
1523 dib8000_write_word(state, 1288, reg_1288);
1528 struct dib8000_state *state = fe->demodulator_priv;
1536 dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
1540 reg_1287 = dib8000_read_word(state, 1287);
1545 dib8000_write_word(state, 1287, reg_1287);
1547 state->input_mode_mpeg = 1;
1552 dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
1553 state->input_mode_mpeg = 0;
1557 dib8000_set_diversity_in(state->fe[0], onoff);
1563 struct dib8000_state *state = fe->demodulator_priv;
1568 state->output_mode = mode;
1569 dib8096p_host_bus_drive(state, 1);
1572 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
1573 outreg = dib8000_read_word(state, 1286) &
1584 dib8096p_configMpegMux(state, 3, 1, 1);
1585 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
1588 dib8096p_setHostBusMux(state,
1597 dib8096p_configMpegMux(state, 2, 0, 0);
1598 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
1601 dib8096p_setHostBusMux(state,
1609 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
1617 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
1625 dib8096p_setDibTxMux(state, DIV_ON_DIBTX);
1626 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1631 dib8096p_setDibTxMux(state, ADC_ON_DIBTX);
1632 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1640 state->cfg.output_mpeg2_in_188_bytes);
1641 if (state->cfg.output_mpeg2_in_188_bytes)
1644 ret |= dib8000_write_word(state, 299, smo_mode);
1646 ret |= dib8000_write_word(state, 299 + 1, fifo_threshold);
1647 ret |= dib8000_write_word(state, 1286, outreg);
1676 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1682 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
1687 dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
1688 dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
1696 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1703 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
1708 dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f));
1712 n_empty = dib8000_read_word(state, 1984)&0x1;
1718 read_word = dib8000_read_word(state, 1987);
1740 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1744 dib8000_write_word(state, apb_address,
1747 word = dib8000_read_word(state, apb_address);
1757 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1848 i = ((dib8000_read_word(state, 921) >> 12)&0x3);
1849 word = dib8000_read_word(state, 924+i);
1859 word = (dib8000_read_word(state, 921) &
1862 dib8000_write_word(state, 921, word);
1893 struct dib8000_state *state = fe->demodulator_priv;
1898 en_cur_state = dib8000_read_word(state, 1922);
1902 state->tuner_enable = en_cur_state ;
1907 if (state->tuner_enable != 0)
1908 en_cur_state = state->tuner_enable;
1911 dib8000_write_word(state, 1922, en_cur_state);
1923 struct dib8000_state *state = fe->demodulator_priv;
1927 val = dib8000_read32(state, 384);
1942 struct dib8000_state *state = fe->demodulator_priv;
1947 val = dib8000_read_word(state, 403);
1950 val = dib8000_read_word(state, 404);
1959 static void dib8000_update_timf(struct dib8000_state *state)
1961 u32 timf = state->timf = dib8000_read32(state, 435);
1963 dib8000_write_word(state, 29, (u16) (timf >> 16));
1964 dib8000_write_word(state, 30, (u16) (timf & 0xffff));
1965 dprintk("Updated timing frequency: %d (default: %d)\n", state->timf, state->timf_default);
1970 struct dib8000_state *state = fe->demodulator_priv;
1974 state->timf = timf;
1977 dib8000_update_timf(state);
1982 dib8000_set_bandwidth(state->fe[0], 6000);
1984 return state->timf;
1993 static u16 dib8000_set_layer(struct dib8000_state *state, u8 layer_index, u16 max_constellation)
1996 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2037 dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment_count & 0xf) << 6) | (cr << 3) | time_intlv);
2058 static u16 dib8000_adp_fine_tune(struct dib8000_state *state, u16 max_constellation)
2080 dib8000_write_word(state, 215 + i, adp[i]);
2085 static void dib8000_update_ana_gain(struct dib8000_state *state, u16 ana_gain)
2089 dib8000_write_word(state, 116, ana_gain);
2094 dib8000_write_word(state, 80 + i, adc_target_16dB[i]);
2097 dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355);
2101 static void dib8000_load_ana_fe_coefs(struct dib8000_state *state, const s16 *ana_fe)
2105 if (state->isdbt_cfg_loaded == 0)
2107 dib8000_write_word(state, 117 + mode, ana_fe[mode]);
2134 static u16 dib8000_get_init_prbs(struct dib8000_state *state, u16 subchannel)
2143 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
2161 static void dib8000_set_13seg_channel(struct dib8000_state *state)
2166 state->seg_mask = 0x1fff; /* All 13 segments enabled */
2169 if (state->isdbt_cfg_loaded == 0) { /* if not Sound Broadcasting mode : put default values for 13 segments */
2170 dib8000_write_word(state, 180, (16 << 6) | 9);
2171 dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2);
2174 dib8000_write_word(state, 181+i, coff_pow);
2178 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1);
2181 dib8000_write_word(state, 340, (8 << 6) | (6 << 0));
2183 dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
2185 dib8000_write_word(state, 228, 0); /* default value */
2186 dib8000_write_word(state, 265, 31); /* default value */
2187 dib8000_write_word(state, 205, 0x200f); /* init value */
2195 if (state->cfg.pll->ifreq == 0)
2196 dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */
2198 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_13seg);
2201 static void dib8000_set_subchannel_prbs(struct dib8000_state *state, u16 init_prbs)
2205 reg_1 = dib8000_read_word(state, 1);
2206 dib8000_write_word(state, 1, (init_prbs << 2) | (reg_1 & 0x3)); /* ADDR 1 */
2209 static void dib8000_small_fine_tune(struct dib8000_state *state)
2213 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2215 dib8000_write_word(state, 352, state->seg_diff_mask);
2216 dib8000_write_word(state, 353, state->seg_mask);
2219 dib8000_write_word(state, 351, (c->isdbt_sb_mode << 9) | (c->isdbt_sb_mode << 8) | (13 << 4) | 5);
2289 dib8000_write_word(state, 343 + i, ncoeff[i]);
2295 static void dib8000_set_sb_channel(struct dib8000_state *state)
2297 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2302 dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); /* adp_pass =1 */
2303 dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); /* pha3_force_pha_shift = 1 */
2305 dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); /* adp_pass =0 */
2306 dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); /* pha3_force_pha_shift = 0 */
2310 state->seg_mask = 0x00E0;
2312 state->seg_mask = 0x0040;
2314 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
2318 dib8000_write_word(state, 187, (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~c->isdbt_partial_reception & 1) << 2) | 0x3);
2320 dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); /* P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8 */
2321 dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));/* P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1 */
2326 if (state->mode == 3)
2327 dib8000_write_word(state, 180, 0x1fcf | ((state->mode - 1) << 14));
2329 dib8000_write_word(state, 180, 0x0fcf | ((state->mode - 1) << 14));
2332 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4);
2335 dib8000_write_word(state, 180, 0x1fcf | (1 << 14));
2337 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4);
2341 dib8000_write_word(state, 228, 1); /* P_2d_mode_byp=1 */
2342 dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); /* P_cspu_win_cut = 0 */
2345 dib8000_write_word(state, 265, 15); /* P_equal_noise_sel = 15 */
2349 dib8000_write_word(state, 181+i, coff[i]);
2350 dib8000_write_word(state, 184+i, coff[i]);
2358 dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask); /* P_equal_noise_seg_inh */
2361 dib8000_write_word(state, 178, 64); /* P_fft_powrange = 64 */
2363 dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */
2366 static void dib8000_set_isdbt_common_channel(struct dib8000_state *state, u8 seq, u8 autosearching)
2372 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2378 dib8000_write_word(state, 10, (seq << 4));
2381 state->mode = fft_to_mode(state);
2384 tmp = dib8000_read_word(state, 1);
2385 dib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3));
2387 dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_reception & 1) << 5) | ((c->isdbt_sb_mode & 1) << 4));
2391 state->seg_diff_mask = (c->layer[0].modulation == DQPSK) << permu_seg[0];
2395 state->seg_diff_mask |= 1 << permu_seg[i+1];
2400 state->seg_diff_mask |= 1 << permu_seg[i];
2403 if (state->seg_diff_mask)
2404 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
2406 dib8000_write_word(state, 268, (2 << 9) | 39); /*init value */
2409 max_constellation = dib8000_set_layer(state, i, max_constellation);
2411 state->layer_b_nb_seg = c->layer[1].segment_count;
2412 state->layer_c_nb_seg = c->layer[2].segment_count;
2416 dib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask);
2418 state->differential_constellation = (state->seg_diff_mask != 0);
2421 ana_gain = dib8000_adp_fine_tune(state, max_constellation);
2424 dib8000_update_ana_gain(state, ana_gain);
2428 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_3seg);
2430 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_1seg); /* 1-segment */
2434 dib8000_set_sb_channel(state);
2435 init_prbs = dib8000_get_init_prbs(state,
2438 dib8000_set_13seg_channel(state);
2443 dib8000_small_fine_tune(state);
2445 dib8000_set_subchannel_prbs(state, init_prbs);
2449 if ((((~state->seg_diff_mask) >> i) & 1) == 1) {
2450 p_cfr_left_edge += (1 << i) * ((i == 0) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i - 1)) & 1) == 0));
2451 p_cfr_right_edge += (1 << i) * ((i == 12) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i + 1)) & 1) == 0));
2454 dib8000_write_word(state, 222, p_cfr_left_edge); /* p_cfr_left_edge */
2455 dib8000_write_word(state, 223, p_cfr_right_edge); /* p_cfr_right_edge */
2458 dib8000_write_word(state, 189, ~state->seg_mask | state->seg_diff_mask); /* P_lmod4_seg_inh */
2459 dib8000_write_word(state, 192, ~state->seg_mask | state->seg_diff_mask); /* P_pha3_seg_inh */
2460 dib8000_write_word(state, 225, ~state->seg_mask | state->seg_diff_mask); /* P_tac_seg_inh */
2463 dib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */
2465 dib8000_write_word(state, 288, 0x1fff); /*disable equalisation of the tmcc when autosearch to be able to find the DQPSK channels. */
2467 dib8000_write_word(state, 211, state->seg_mask & (~state->seg_diff_mask)); /* P_des_seg_enabled */
2468 dib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */
2470 dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */
2479 dib8000_write_word(state, 290, tmcc_pow); /* P_tmcc_dec_thres_2k */
2480 dib8000_write_word(state, 291, tmcc_pow); /* P_tmcc_dec_thres_4k */
2481 dib8000_write_word(state, 292, tmcc_pow); /* P_tmcc_dec_thres_8k */
2482 /*dib8000_write_word(state, 287, (1 << 13) | 0x1000 ); */
2485 if (state->isdbt_cfg_loaded == 0)
2486 dib8000_write_word(state, 250, 3285); /* p_2d_hspeed_thr0 */
2488 state->isdbt_cfg_loaded = 0;
2491 static u32 dib8000_wait_lock(struct dib8000_state *state, u32 internal,
2499 if (state->revision == 0x8090)
2507 dib8000_write_word(state, reg, (u16)((value >> 16) & 0xffff));
2508 dib8000_write_word(state, (reg + 1), (u16)(value & 0xffff));
2515 struct dib8000_state *state = fe->demodulator_priv;
2516 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2518 u32 value, internal = state->cfg.pll->internal;
2520 if (state->revision == 0x8090)
2521 internal = dib8000_read32(state, 23) / 1000;
2523 if ((state->revision >= 0x8002) &&
2524 (state->autosearch_state == AS_SEARCHING_FFT)) {
2525 dib8000_write_word(state, 37, 0x0065); /* P_ctrl_pha_off_max default values */
2526 dib8000_write_word(state, 116, 0x0000); /* P_ana_gain to 0 */
2528 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x1fff) | (0 << 13) | (1 << 15)); /* P_mode = 0, P_restart_search=1 */
2529 dib8000_write_word(state, 1, (dib8000_read_word(state, 1) & 0xfffc) | 0); /* P_guard = 0 */
2530 dib8000_write_word(state, 6, 0); /* P_lock0_mask = 0 */
2531 dib8000_write_word(state, 7, 0); /* P_lock1_mask = 0 */
2532 dib8000_write_word(state, 8, 0); /* P_lock2_mask = 0 */
2533 dib8000_write_word(state, 10, (dib8000_read_word(state, 10) & 0x200) | (16 << 4) | (0 << 0)); /* P_search_list=16, P_search_maxtrial=0 */
2535 if (state->revision == 0x8090)
2536 value = dib8000_wait_lock(state, internal, 10, 10, 10); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2538 value = dib8000_wait_lock(state, internal, 20, 20, 20); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2540 dib8000_write_word(state, 17, 0);
2541 dib8000_write_word(state, 18, 200); /* P_search_rstst = 200 */
2542 dib8000_write_word(state, 19, 0);
2543 dib8000_write_word(state, 20, 400); /* P_search_rstend = 400 */
2544 dib8000_write_word(state, 21, (value >> 16) & 0xffff); /* P_search_checkst */
2545 dib8000_write_word(state, 22, value & 0xffff);
2547 if (state->revision == 0x8090)
2548 dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (0 << 8)); /* P_corm_alpha = 0 */
2550 dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (9 << 8)); /* P_corm_alpha = 3 */
2551 dib8000_write_word(state, 355, 2); /* P_search_param_max = 2 */
2554 dib8000_write_word(state, 356, 0);
2555 dib8000_write_word(state, 357, 0x111);
2557 dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (1 << 13)); /* P_restart_ccg = 1 */
2558 dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (0 << 13)); /* P_restart_ccg = 0 */
2559 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x7ff) | (0 << 15) | (1 << 13)); /* P_restart_search = 0; */
2560 } else if ((state->revision >= 0x8002) &&
2561 (state->autosearch_state == AS_SEARCHING_GUARD)) {
2571 c->transmission_mode = state->found_nfft;
2573 dib8000_set_isdbt_common_channel(state, slist, 1);
2576 dib8000_write_word(state, 6, 0x4);
2577 if (state->revision == 0x8090)
2578 dib8000_write_word(state, 7, ((1 << 12) | (1 << 11) | (1 << 10)));/* tmcc_dec_lock, tmcc_sync_lock, tmcc_data_lock, tmcc_bch_uncor */
2580 dib8000_write_word(state, 7, 0x8);
2581 dib8000_write_word(state, 8, 0x1000);
2584 if (state->revision == 0x8090)
2585 dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2587 dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2589 dib8000_write_word(state, 355, 3); /* P_search_param_max = 3 */
2592 dib8000_write_word(state, 356, 0);
2593 dib8000_write_word(state, 357, 0xf);
2595 value = dib8000_read_word(state, 0);
2596 dib8000_write_word(state, 0, (u16)((1 << 15) | value));
2597 dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */
2598 dib8000_write_word(state, 0, (u16)value);
2611 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));
2618 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 to have autosearch start ok with mode2 */
2627 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 */
2634 dib8000_set_isdbt_common_channel(state, slist, 1);
2637 dib8000_write_word(state, 6, 0x4);
2638 if (state->revision == 0x8090)
2639 dib8000_write_word(state, 7, (1 << 12) | (1 << 11) | (1 << 10));
2641 dib8000_write_word(state, 7, 0x8);
2642 dib8000_write_word(state, 8, 0x1000);
2645 if (state->revision == 0x8090)
2646 dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2648 dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2650 value = dib8000_read_word(state, 0);
2651 dib8000_write_word(state, 0, (u16)((1 << 15) | value));
2652 dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */
2653 dib8000_write_word(state, 0, (u16)value);
2660 struct dib8000_state *state = fe->demodulator_priv;
2661 u16 irq_pending = dib8000_read_word(state, 1284);
2663 if ((state->revision >= 0x8002) &&
2664 (state->autosearch_state == AS_SEARCHING_FFT)) {
2684 static void dib8000_viterbi_state(struct dib8000_state *state, u8 onoff)
2688 tmp = dib8000_read_word(state, 771);
2690 dib8000_write_word(state, 771, tmp & 0xfffd);
2692 dib8000_write_word(state, 771, tmp | (1<<1));
2695 static void dib8000_set_dds(struct dib8000_state *state, s32 offset_khz)
2699 u32 dds = state->cfg.pll->ifreq & 0x1ffffff;
2700 u8 invert = !!(state->cfg.pll->ifreq & (1 << 25));
2703 if (state->revision == 0x8090) {
2705 unit_khz_dds_val = (1<<26) / (dib8000_read32(state, 23) / 1000);
2715 unit_khz_dds_val = (u16) (67108864 / state->cfg.pll->internal);
2729 if (abs_offset_khz <= (state->cfg.pll->internal / ratio)) {
2731 dib8000_write_word(state, 26, invert);
2732 dib8000_write_word(state, 27, (u16)(dds >> 16) & 0x1ff);
2733 dib8000_write_word(state, 28, (u16)(dds & 0xffff));
2737 static void dib8000_set_frequency_offset(struct dib8000_state *state)
2739 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2744 if (state->fe[0]->ops.tuner_ops.get_frequency)
2745 state->fe[0]->ops.tuner_ops.get_frequency(state->fe[0], ¤t_rf);
2752 state->subchannel = c->isdbt_sb_subchannel;
2754 i = dib8000_read_word(state, 26) & 1; /* P_dds_invspec */
2755 dib8000_write_word(state, 26, c->inversion ^ i);
2757 if (state->cfg.pll->ifreq == 0) { /* low if tuner */
2759 dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1);
2769 dib8000_set_dds(state, total_dds_offset_khz);
2774 static u32 dib8000_get_symbol_duration(struct dib8000_state *state)
2776 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2796 static void dib8000_set_isdbt_loop_params(struct dib8000_state *state, enum param_loop_step loop_step)
2798 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2805 reg_32 = ((11 - state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x40 */
2806 reg_37 = (3 << 5) | (0 << 4) | (10 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (10-P_mode) */
2808 reg_32 = ((10 - state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (10-P_mode), P_corm_alpha=6, P_corm_thres=0x60 */
2809 reg_37 = (3 << 5) | (0 << 4) | (9 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (9-P_mode) */
2812 reg_32 = ((9 - state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */
2813 reg_37 = (3 << 5) | (0 << 4) | (8 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = 9 */
2819 reg_32 = ((13-state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40*/
2820 reg_37 = (12-state->mode) | ((5 + state->mode) << 5);
2822 reg_32 = ((12-state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (12-P_mode) , P_corm_alpha=6, P_corm_thres=0x60 */
2823 reg_37 = (11-state->mode) | ((5 + state->mode) << 5);
2826 reg_32 = ((11-state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_thres=0x80 */
2827 reg_37 = ((5+state->mode) << 5) | (10 - state->mode);
2831 dib8000_write_word(state, 32, reg_32);
2832 dib8000_write_word(state, 37, reg_37);
2835 static void dib8000_demod_restart(struct dib8000_state *state)
2837 dib8000_write_word(state, 770, 0x4000);
2838 dib8000_write_word(state, 770, 0x0000);
2842 static void dib8000_set_sync_wait(struct dib8000_state *state)
2844 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2861 if (state->cfg.diversity_delay == 0)
2864 sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + state->cfg.diversity_delay; /* add 50% SFN margin + compensate for DVSY-fifo */
2866 dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | (sync_wait << 4));
2869 static unsigned long dib8000_get_timeout(struct dib8000_state *state, u32 delay, enum timeout_mode mode)
2872 delay *= state->symbol_duration;
2879 struct dib8000_state *state = fe->demodulator_priv;
2880 return state->status;
2885 struct dib8000_state *state = fe->demodulator_priv;
2886 return state->tune_state;
2891 struct dib8000_state *state = fe->demodulator_priv;
2893 state->tune_state = tune_state;
2899 struct dib8000_state *state = fe->demodulator_priv;
2901 state->status = FE_STATUS_TUNE_PENDING;
2902 state->tune_state = CT_DEMOD_START;
2908 struct dib8000_state *state = fe->demodulator_priv;
2910 if (state->revision == 0x8090)
2911 return dib8000_read_word(state, 570);
2912 return dib8000_read_word(state, 568);
2915 static int dib8090p_init_sdram(struct dib8000_state *state)
2920 reg = dib8000_read_word(state, 274) & 0xfff0;
2921 dib8000_write_word(state, 274, reg | 0x7); /* P_dintlv_delay_ram = 7 because of MobileSdram */
2923 dib8000_write_word(state, 1803, (7 << 2));
2925 reg = dib8000_read_word(state, 1280);
2926 dib8000_write_word(state, 1280, reg | (1 << 2)); /* force restart P_restart_sdram */
2927 dib8000_write_word(state, 1280, reg); /* release restart P_restart_sdram */
2940 * On manual mode, the current dib8000_tune state machine is very restrict:
3019 struct dib8000_state *state = fe->demodulator_priv;
3020 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
3021 enum frontend_tune_state *tune_state = &state->tune_state;
3026 unsigned long *timeout = &state->timeout;
3039 state->channel_parameters_set, *tune_state, state->autosearch_state, now);
3046 if (state->revision == 0x8090)
3047 dib8090p_init_sdram(state);
3048 state->status = FE_STATUS_TUNE_PENDING;
3049 state->channel_parameters_set = is_manual_mode(c);
3052 state->channel_parameters_set ? "manual" : "auto");
3054 dib8000_viterbi_state(state, 0); /* force chan dec in restart */
3057 dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60);
3059 dib8000_set_frequency_offset(state);
3062 if (state->channel_parameters_set == 0) { /* The channel struct is unknown, search it ! */
3064 if (state->revision != 0x8090) {
3065 state->agc1_max = dib8000_read_word(state, 108);
3066 state->agc1_min = dib8000_read_word(state, 109);
3067 state->agc2_max = dib8000_read_word(state, 110);
3068 state->agc2_min = dib8000_read_word(state, 111);
3069 agc1 = dib8000_read_word(state, 388);
3070 agc2 = dib8000_read_word(state, 389);
3071 dib8000_write_word(state, 108, agc1);
3072 dib8000_write_word(state, 109, agc1);
3073 dib8000_write_word(state, 110, agc2);
3074 dib8000_write_word(state, 111, agc2);
3077 state->autosearch_state = AS_SEARCHING_FFT;
3078 state->found_nfft = TRANSMISSION_MODE_AUTO;
3079 state->found_guard = GUARD_INTERVAL_AUTO;
3082 state->autosearch_state = AS_DONE;
3085 state->symbol_duration = dib8000_get_symbol_duration(state);
3090 if (state->revision == 0x8090)
3100 state->status = FE_STATUS_TUNE_FAILED;
3101 state->autosearch_state = AS_DONE;
3105 state->status = FE_STATUS_FFT_SUCCESS; /* signal to the upper layer, that there was a channel found and the parameters can be read */
3107 if (state->autosearch_state == AS_SEARCHING_GUARD)
3110 state->autosearch_state = AS_DONE;
3119 switch (state->autosearch_state) {
3122 if (state->revision == 0x8090) {
3123 corm[2] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));
3124 corm[1] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));
3125 corm[0] = (dib8000_read_word(state, 600) << 16) | (dib8000_read_word(state, 601));
3127 corm[2] = (dib8000_read_word(state, 594) << 16) | (dib8000_read_word(state, 595));
3128 corm[1] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));
3129 corm[0] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));
3141 state->found_nfft = TRANSMISSION_MODE_2K;
3144 state->found_nfft = TRANSMISSION_MODE_4K;
3148 state->found_nfft = TRANSMISSION_MODE_8K;
3154 state->autosearch_state = AS_SEARCHING_GUARD;
3155 if (state->revision == 0x8090)
3162 if (state->revision == 0x8090)
3163 state->found_guard = dib8000_read_word(state, 572) & 0x3;
3165 state->found_guard = dib8000_read_word(state, 570) & 0x3;
3166 /* dprintk("guard interval found=%i\n", state->found_guard); */
3171 /* the demod should never be in this state */
3172 state->status = FE_STATUS_TUNE_FAILED;
3173 state->autosearch_state = AS_DONE;
3180 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_1);
3181 dib8000_set_isdbt_common_channel(state, 0, 0);/* setting the known channel parameters here */
3186 dib8000_demod_restart(state);
3188 dib8000_set_sync_wait(state);
3189 dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);
3191 locks = (dib8000_read_word(state, 180) >> 6) & 0x3f; /* P_coff_winlen ? */
3193 *timeout = dib8000_get_timeout(state, 2 * locks, SYMBOL_DEPENDENT_ON);
3200 dib8000_update_timf(state); /* we achieved a coff_cpil_lock - it's time to update the timf */
3201 if (!state->differential_constellation) {
3203 *timeout = dib8000_get_timeout(state, (20 * ((dib8000_read_word(state, 188)>>5)&0x1f)), SYMBOL_DEPENDENT_ON);
3214 if ((state->fe[1] != NULL) && (state->output_mode != OUTMODE_DIVERSITY)) {
3216 if (dib8000_get_status(state->fe[1]) <= FE_STATUS_STD_SUCCESS) /* Something is locked on the input fe */
3218 else if (dib8000_get_status(state->fe[1]) >= FE_STATUS_TUNE_TIME_TOO_SHORT) { /* fe in input failed also, break the current one */
3220 dib8000_viterbi_state(state, 1); /* start viterbi chandec */
3221 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);
3222 state->status = FE_STATUS_TUNE_FAILED;
3225 dib8000_viterbi_state(state, 1); /* start viterbi chandec */
3226 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);
3228 state->status = FE_STATUS_TUNE_FAILED;
3242 dib8000_viterbi_state(state, 1); /* start viterbi chandec */
3243 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);
3248 && !state->differential_constellation) {
3249 state->subchannel = 0;
3253 state->status = FE_STATUS_LOCKED;
3258 if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable of deinterleaving : esram */
3265 state->longest_intlv_layer = i;
3277 if (state->diversity_onoff != 0) /* because of diversity sync */
3282 deeper_interleaver, state->longest_intlv_layer, locks, *timeout);
3291 if (locks&(1<<(7-state->longest_intlv_layer))) { /* mpeg lock : check the longest one */
3298 && !state->differential_constellation)
3300 state->status = FE_STATUS_DEMOD_SUCCESS;
3302 state->status = FE_STATUS_DATA_LOCKED;
3307 && !state->differential_constellation) { /* continue to try init prbs autosearch */
3308 state->subchannel += 3;
3318 state->status = FE_STATUS_DATA_LOCKED;
3320 state->status = FE_STATUS_TUNE_FAILED;
3327 init_prbs = dib8000_get_init_prbs(state, state->subchannel);
3330 dib8000_set_subchannel_prbs(state, init_prbs);
3334 state->status = FE_STATUS_TUNE_FAILED;
3346 if ((state->revision != 0x8090) && (state->agc1_max != 0)) {
3347 dib8000_write_word(state, 108, state->agc1_max);
3348 dib8000_write_word(state, 109, state->agc1_min);
3349 dib8000_write_word(state, 110, state->agc2_max);
3350 dib8000_write_word(state, 111, state->agc2_min);
3351 state->agc1_max = 0;
3352 state->agc1_min = 0;
3353 state->agc2_max = 0;
3354 state->agc2_min = 0;
3364 return ret * state->symbol_duration;
3365 if ((ret > 0) && (ret < state->symbol_duration))
3366 return state->symbol_duration; /* at least one symbol */
3372 struct dib8000_state *state = fe->demodulator_priv;
3376 dib8000_set_power_mode(state, DIB8000_POWER_ALL);
3377 dib8000_set_adc_state(state, DIBX000_ADC_ON);
3378 if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
3381 if (state->revision == 0x8090)
3382 dib8000_sad_calib(state);
3384 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3385 ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]);
3395 struct dib8000_state *state = fe->demodulator_priv;
3399 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3400 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
3405 if (state->revision != 0x8090)
3407 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
3408 return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_ADC_OFF);
3416 struct dib8000_state *state = fe->demodulator_priv;
3433 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3434 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
3438 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], c);
3439 for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
3441 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
3442 state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
3443 state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
3444 state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
3445 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
3447 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
3448 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
3449 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
3450 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
3458 c->isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;
3460 if (state->revision == 0x8090)
3461 val = dib8000_read_word(state, 572);
3463 val = dib8000_read_word(state, 570);
3500 val = dib8000_read_word(state, 505);
3507 val = dib8000_read_word(state, 493 + i) & 0x0f;
3519 val = dib8000_read_word(state, 499 + i) & 0x3;
3528 val = dib8000_read_word(state, 481 + i);
3557 val = dib8000_read_word(state, 487 + i);
3584 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3585 state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = c->isdbt_sb_mode;
3586 state->fe[index_frontend]->dtv_property_cache.inversion = c->inversion;
3587 state->fe[index_frontend]->dtv_property_cache.transmission_mode = c->transmission_mode;
3588 state->fe[index_frontend]->dtv_property_cache.guard_interval = c->guard_interval;
3589 state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = c->isdbt_partial_reception;
3591 state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = c->layer[i].segment_count;
3592 state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = c->layer[i].interleaving;
3593 state->fe[index_frontend]->dtv_property_cache.layer[i].fec = c->layer[i].fec;
3594 state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = c->layer[i].modulation;
3602 struct dib8000_state *state = fe->demodulator_priv;
3603 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
3618 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3620 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT;
3621 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
3624 if (state->revision != 0x8090) {
3625 dib8000_set_diversity_in(state->fe[index_frontend], 1);
3627 dib8000_set_output_mode(state->fe[index_frontend],
3630 dib8000_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);
3632 dib8096p_set_diversity_in(state->fe[index_frontend], 1);
3634 dib8096p_set_output_mode(state->fe[index_frontend],
3637 dib8096p_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);
3641 if (state->fe[index_frontend]->ops.tuner_ops.set_params)
3642 state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]);
3644 dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START);
3648 if (state->revision != 0x8090)
3649 dib8000_set_diversity_in(state->fe[index_frontend - 1], 0);
3651 dib8096p_set_diversity_in(state->fe[index_frontend - 1], 0);
3655 time = dib8000_agc_startup(state->fe[0]);
3656 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3657 time_slave = dib8000_agc_startup(state->fe[index_frontend]);
3677 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3678 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) {
3685 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3686 dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
3691 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3692 delay = dib8000_tune(state->fe[index_frontend]);
3700 if (state->channel_parameters_set == 0) { /* searching */
3701 if ((dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_DEMOD_SUCCESS) || (dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_FFT_SUCCESS)) {
3703 dib8000_get_frontend(state->fe[index_frontend], c); /* we read the channel parameters from the frontend which was successful */
3704 state->channel_parameters_set = 1;
3706 for (l = 0; (l < MAX_NUMBER_OF_FRONTENDS) && (state->fe[l] != NULL); l++) {
3709 dib8000_tune_restart_from_demod(state->fe[l]);
3711 state->fe[l]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
3712 state->fe[l]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
3713 state->fe[l]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
3714 state->fe[l]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
3715 state->fe[l]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
3717 state->fe[l]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
3718 state->fe[l]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
3719 state->fe[l]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
3720 state->fe[l]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
3729 if (dib8000_get_status(state->fe[0]) == FE_STATUS_TUNE_FAILED ||
3730 dib8000_get_status(state->fe[0]) == FE_STATUS_LOCKED ||
3731 dib8000_get_status(state->fe[0]) == FE_STATUS_DATA_LOCKED) {
3734 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3735 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_DEMOD_STOP)
3739 dprintk("tuning done with status %d\n", dib8000_get_status(state->fe[0]));
3752 if (state->revision != 0x8090)
3753 dib8000_set_output_mode(state->fe[0], state->cfg.output_mode);
3755 dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode);
3756 if (state->cfg.enMpegOutput == 0) {
3757 dib8096p_setDibTxMux(state, MPEG_ON_DIBTX);
3758 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
3769 struct dib8000_state *state = fe->demodulator_priv;
3774 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3775 lock_slave |= dib8000_read_lock(state->fe[index_frontend]);
3792 lock = dib8000_read_word(state, 554); /* Viterbi Layer A */
3796 lock = dib8000_read_word(state, 555); /* Viterbi Layer B */
3800 lock = dib8000_read_word(state, 556); /* Viterbi Layer C */
3811 struct dib8000_state *state = fe->demodulator_priv;
3814 if (state->revision == 0x8090)
3815 *ber = (dib8000_read_word(state, 562) << 16) |
3816 dib8000_read_word(state, 563);
3818 *ber = (dib8000_read_word(state, 560) << 16) |
3819 dib8000_read_word(state, 561);
3825 struct dib8000_state *state = fe->demodulator_priv;
3828 if (state->revision == 0x8090)
3829 *unc = dib8000_read_word(state, 567);
3831 *unc = dib8000_read_word(state, 565);
3837 struct dib8000_state *state = fe->demodulator_priv;
3842 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3843 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
3850 val = 65535 - dib8000_read_word(state, 390);
3860 struct dib8000_state *state = fe->demodulator_priv;
3864 if (state->revision != 0x8090)
3865 val = dib8000_read_word(state, 542);
3867 val = dib8000_read_word(state, 544);
3874 if (state->revision != 0x8090)
3875 val = dib8000_read_word(state, 543);
3877 val = dib8000_read_word(state, 545);
3893 struct dib8000_state *state = fe->demodulator_priv;
3898 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3899 snr_master += dib8000_get_snr(state->fe[index_frontend]);
4009 struct dib8000_state *state = fe->demodulator_priv;
4010 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
4123 struct dib8000_state *state = fe->demodulator_priv;
4124 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
4156 if (time_after(jiffies, state->per_jiffies_stats)) {
4157 state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000);
4162 if (state->fe[i])
4163 snr += dib8000_get_snr(state->fe[i]);
4178 if (val < state->init_ucb)
4179 state->init_ucb += 0x100000000LL;
4182 c->block_error.stat[0].uvalue = val + state->init_ucb;
4199 if (time_after(jiffies, state->ber_jiffies_stats)) {
4201 state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
4213 if (state->revision < 0x8002)
4228 if (time_after(jiffies, state->ber_jiffies_stats_layer[i])) {
4231 state->ber_jiffies_stats_layer[i] = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
4235 val = dib8000_read_word(state, per_layer_regs[i].ber);
4244 val = dib8000_read_word(state, per_layer_regs[i].per);
4264 struct dib8000_state *state = fe->demodulator_priv;
4267 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
4271 state->fe[index_frontend] = fe_slave;
4281 struct dib8000_state *state = fe->demodulator_priv;
4285 return state->fe[slave_index];
4443 struct dib8000_state *state;
4447 state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL);
4448 if (state == NULL)
4454 memcpy(&state->cfg, cfg, sizeof(struct dib8000_config));
4455 state->i2c.adap = i2c_adap;
4456 state->i2c.addr = i2c_addr;
4457 state->i2c.i2c_write_buffer = state->i2c_write_buffer;
4458 state->i2c.i2c_read_buffer = state->i2c_read_buffer;
4459 mutex_init(&state->i2c_buffer_lock);
4460 state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock;
4461 state->gpio_val = cfg->gpio_val;
4462 state->gpio_dir = cfg->gpio_dir;
4467 if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
4468 state->cfg.output_mode = OUTMODE_MPEG2_FIFO;
4470 state->fe[0] = fe;
4471 fe->demodulator_priv = state;
4472 memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops));
4474 state->timf_default = cfg->pll->timf;
4476 if (dib8000_identify(&state->i2c) == 0) {
4481 dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr);
4484 strscpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface",
4485 sizeof(state->dib8096p_tuner_adap.name));
4486 state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo;
4487 state->dib8096p_tuner_adap.algo_data = NULL;
4488 state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent;
4489 i2c_set_adapdata(&state->dib8096p_tuner_adap, state);
4490 i2c_add_adapter(&state->dib8096p_tuner_adap);
4494 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len = 3 */
4495 state->current_demod_bw = 6000;
4500 kfree(state);