Lines Matching refs:pll_prediv
700 (pll->pll_prediv << 8) | (pll->pll_ratio << 0));
731 (pll->pll_prediv));
750 u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ;
757 if ((pll == NULL) || (pll->pll_prediv == prediv &&
761 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio);
770 (pll->pll_prediv & 0x3f));
776 internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio;
796 dprintk("PLL: Bandwidth Change %d MHz -> %d MHz (prediv: %d->%d)\n", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv);
798 if (state->cfg.pll->pll_prediv != oldprediv) {
802 dprintk("PLL: New Setting for %d MHz Bandwidth (prediv: %d, ratio: %d)\n", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_ratio);
814 dprintk("PLL: Update ratio (prediv: %d, ratio: %d)\n", state->cfg.pll->pll_prediv, ratio);
815 dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL ratio is updated. */