Lines Matching refs:state
76 static u16 dib7000m_read_word(struct dib7000m_state *state, u16 reg)
80 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
85 state->i2c_write_buffer[0] = (reg >> 8) | 0x80;
86 state->i2c_write_buffer[1] = reg & 0xff;
88 memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
89 state->msg[0].addr = state->i2c_addr >> 1;
90 state->msg[0].flags = 0;
91 state->msg[0].buf = state->i2c_write_buffer;
92 state->msg[0].len = 2;
93 state->msg[1].addr = state->i2c_addr >> 1;
94 state->msg[1].flags = I2C_M_RD;
95 state->msg[1].buf = state->i2c_read_buffer;
96 state->msg[1].len = 2;
98 if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2)
101 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
102 mutex_unlock(&state->i2c_buffer_lock);
107 static int dib7000m_write_word(struct dib7000m_state *state, u16 reg, u16 val)
111 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
116 state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
117 state->i2c_write_buffer[1] = reg & 0xff;
118 state->i2c_write_buffer[2] = (val >> 8) & 0xff;
119 state->i2c_write_buffer[3] = val & 0xff;
121 memset(&state->msg[0], 0, sizeof(struct i2c_msg));
122 state->msg[0].addr = state->i2c_addr >> 1;
123 state->msg[0].flags = 0;
124 state->msg[0].buf = state->i2c_write_buffer;
125 state->msg[0].len = 4;
127 ret = (i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ?
129 mutex_unlock(&state->i2c_buffer_lock);
132 static void dib7000m_write_tab(struct dib7000m_state *state, u16 *buf)
140 if (state->reg_offs && (r >= 112 && r <= 331)) // compensate for 7000MC
144 dib7000m_write_word(state, r, *n++);
151 static int dib7000m_set_output_mode(struct dib7000m_state *state, int mode)
159 smo_mode = (dib7000m_read_word(state, 294 + state->reg_offs) & 0x0010) | (1 << 1);
161 dprintk("setting output mode for demod %p to %d\n", &state->demod, mode);
174 if (state->cfg.hostbus_diversity)
188 dprintk("Unhandled output_mode passed to be set for demod %p\n", &state->demod);
192 if (state->cfg.output_mpeg2_in_188_bytes)
195 ret |= dib7000m_write_word(state, 294 + state->reg_offs, smo_mode);
196 ret |= dib7000m_write_word(state, 295 + state->reg_offs, fifo_threshold); /* synchronous fread */
197 ret |= dib7000m_write_word(state, 1795, outreg);
198 ret |= dib7000m_write_word(state, 1805, sram);
200 if (state->revision == 0x4003) {
201 u16 clk_cfg1 = dib7000m_read_word(state, 909) & 0xfffd;
204 dib7000m_write_word(state, 909, clk_cfg1);
209 static void dib7000m_set_power_mode(struct dib7000m_state *state, enum dib7000m_power_mode mode)
245 if (!state->cfg.mobile_mode)
249 if (state->revision != 0x4000)
252 if (state->revision == 0x4003)
255 dib7000m_write_word(state, 903 + offset, reg_903);
256 dib7000m_write_word(state, 904 + offset, reg_904);
257 dib7000m_write_word(state, 905 + offset, reg_905);
258 dib7000m_write_word(state, 906 + offset, reg_906);
261 static int dib7000m_set_adc_state(struct dib7000m_state *state, enum dibx000_adc_states no)
264 u16 reg_913 = dib7000m_read_word(state, 913),
265 reg_914 = dib7000m_read_word(state, 914);
270 ret |= dib7000m_write_word(state, 914, reg_914);
279 if (state->revision == 0x4000) { // workaround for PA/MA
281 dib7000m_write_word(state, 913, 0);
282 dib7000m_write_word(state, 914, reg_914 & 0x3);
284 dib7000m_write_word(state, 913, (1 << 15));
285 dib7000m_write_word(state, 914, reg_914 & 0x3);
310 ret |= dib7000m_write_word(state, 913, reg_913);
311 ret |= dib7000m_write_word(state, 914, reg_914);
316 static int dib7000m_set_bandwidth(struct dib7000m_state *state, u32 bw)
324 state->current_bandwidth = bw;
326 if (state->timf == 0) {
328 timf = state->timf_default;
331 timf = state->timf;
336 dib7000m_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
337 dib7000m_write_word(state, 24, (u16) ((timf ) & 0xffff));
344 struct dib7000m_state *state = demod->demodulator_priv;
346 if (state->div_force_off) {
350 state->div_state = (u8)onoff;
353 dib7000m_write_word(state, 263 + state->reg_offs, 6);
354 dib7000m_write_word(state, 264 + state->reg_offs, 6);
355 dib7000m_write_word(state, 266 + state->reg_offs, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
357 dib7000m_write_word(state, 263 + state->reg_offs, 1);
358 dib7000m_write_word(state, 264 + state->reg_offs, 0);
359 dib7000m_write_word(state, 266 + state->reg_offs, 0);
365 static int dib7000m_sad_calib(struct dib7000m_state *state)
369 // dib7000m_write_word(state, 928, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SAD is writing in set_bandwidth
370 dib7000m_write_word(state, 929, (0 << 1) | (0 << 0));
371 dib7000m_write_word(state, 930, 776); // 0.625*3.3 / 4096
374 dib7000m_write_word(state, 929, (1 << 0));
375 dib7000m_write_word(state, 929, (0 << 0));
382 static void dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_config *bw)
384 dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff));
385 dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000) & 0xffff));
386 dib7000m_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff));
387 dib7000m_write_word(state, 22, (u16) ( bw->ifreq & 0xffff));
389 dib7000m_write_word(state, 928, bw->sad_cfg);
392 static void dib7000m_reset_pll(struct dib7000m_state *state)
394 const struct dibx000_bandwidth_config *bw = state->cfg.bw;
405 if (!state->cfg.quartz_direct) {
409 if(state->cfg.input_clk_is_div_2)
418 dib7000m_write_word(state, 910, reg_910); // pll cfg
419 dib7000m_write_word(state, 907, reg_907); // clk cfg0
420 dib7000m_write_word(state, 908, 0x0006); // clk_cfg1
422 dib7000m_reset_pll_common(state, bw);
425 static void dib7000mc_reset_pll(struct dib7000m_state *state)
427 const struct dibx000_bandwidth_config *bw = state->cfg.bw;
431 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0));
434 //dib7000m_write_word(state, 908, (1 << 14) | (3 << 12) |(0 << 11) |
438 dib7000m_write_word(state, 908, clk_cfg1);
440 dib7000m_write_word(state, 908, clk_cfg1);
443 dib7000m_write_word(state, 910, (1 << 12) | (2 << 10) | (bw->modulo << 8) | (bw->ADClkSrc << 7));
445 dib7000m_reset_pll_common(state, bw);
563 static int dib7000m_demod_reset(struct dib7000m_state *state)
565 dib7000m_set_power_mode(state, DIB7000M_POWER_ALL);
568 dib7000m_set_adc_state(state, DIBX000_VBG_ENABLE);
571 dib7000m_write_word(state, 898, 0xffff);
572 dib7000m_write_word(state, 899, 0xffff);
573 dib7000m_write_word(state, 900, 0xff0f);
574 dib7000m_write_word(state, 901, 0xfffc);
576 dib7000m_write_word(state, 898, 0);
577 dib7000m_write_word(state, 899, 0);
578 dib7000m_write_word(state, 900, 0);
579 dib7000m_write_word(state, 901, 0);
581 if (state->revision == 0x4000)
582 dib7000m_reset_pll(state);
584 dib7000mc_reset_pll(state);
586 if (dib7000m_reset_gpio(state) != 0)
589 if (dib7000m_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
593 dib7000m_write_word(state, 1794, dib7000m_read_word(state, 1794) & ~(1 << 1) );
595 dib7000m_set_bandwidth(state, 8000);
597 dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON);
598 dib7000m_sad_calib(state);
599 dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
601 if (state->cfg.dvbt_mode)
602 dib7000m_write_word(state, 1796, 0x0); // select DVB-T output
604 if (state->cfg.mobile_mode)
605 dib7000m_write_word(state, 261 + state->reg_offs, 2);
607 dib7000m_write_word(state, 224 + state->reg_offs, 1);
610 if(state->cfg.tuner_is_baseband)
611 dib7000m_write_word(state, 36, 0x0755);
613 dib7000m_write_word(state, 36, 0x1f55);
616 if (state->revision == 0x4000)
617 dib7000m_write_word(state, 909, (3 << 10) | (1 << 6));
619 dib7000m_write_word(state, 909, (3 << 4) | 1);
621 dib7000m_write_tab(state, dib7000m_defaults_common);
622 dib7000m_write_tab(state, dib7000m_defaults);
624 dib7000m_set_power_mode(state, DIB7000M_POWER_INTERFACE_ONLY);
626 state->internal_clk = state->cfg.bw->internal;
631 static void dib7000m_restart_agc(struct dib7000m_state *state)
634 dib7000m_write_word(state, 898, 0x0c00);
635 dib7000m_write_word(state, 898, 0x0000);
638 static int dib7000m_agc_soft_split(struct dib7000m_state *state)
642 if(!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0)
646 agc = dib7000m_read_word(state, 390);
648 if (agc > state->current_agc->split.min_thres)
649 split_offset = state->current_agc->split.min;
650 else if (agc < state->current_agc->split.max_thres)
651 split_offset = state->current_agc->split.max;
653 split_offset = state->current_agc->split.max *
654 (agc - state->current_agc->split.min_thres) /
655 (state->current_agc->split.max_thres - state->current_agc->split.min_thres);
660 return dib7000m_write_word(state, 103, (dib7000m_read_word(state, 103) & 0xff00) | split_offset);
663 static int dib7000m_update_lna(struct dib7000m_state *state)
667 if (state->cfg.update_lna) {
669 dyn_gain = dib7000m_read_word(state, 390);
671 if (state->cfg.update_lna(&state->demod,dyn_gain)) { // LNA has changed
672 dib7000m_restart_agc(state);
679 static int dib7000m_set_agc_config(struct dib7000m_state *state, u8 band)
683 if (state->current_band == band && state->current_agc != NULL)
685 state->current_band = band;
687 for (i = 0; i < state->cfg.agc_config_count; i++)
688 if (state->cfg.agc[i].band_caps & band) {
689 agc = &state->cfg.agc[i];
698 state->current_agc = agc;
701 dib7000m_write_word(state, 72 , agc->setup);
702 dib7000m_write_word(state, 73 , agc->inv_gain);
703 dib7000m_write_word(state, 74 , agc->time_stabiliz);
704 dib7000m_write_word(state, 97 , (agc->alpha_level << 12) | agc->thlock);
707 dib7000m_write_word(state, 98, (agc->alpha_mant << 5) | agc->alpha_exp);
708 dib7000m_write_word(state, 99, (agc->beta_mant << 6) | agc->beta_exp);
711 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
714 if (state->wbd_ref != 0)
715 dib7000m_write_word(state, 102, state->wbd_ref);
717 dib7000m_write_word(state, 102, agc->wbd_ref);
719 dib7000m_write_word(state, 103, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8) );
720 dib7000m_write_word(state, 104, agc->agc1_max);
721 dib7000m_write_word(state, 105, agc->agc1_min);
722 dib7000m_write_word(state, 106, agc->agc2_max);
723 dib7000m_write_word(state, 107, agc->agc2_min);
724 dib7000m_write_word(state, 108, (agc->agc1_pt1 << 8) | agc->agc1_pt2 );
725 dib7000m_write_word(state, 109, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
726 dib7000m_write_word(state, 110, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
727 dib7000m_write_word(state, 111, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
729 if (state->revision > 0x4000) { // settings for the MC
730 dib7000m_write_word(state, 71, agc->agc1_pt3);
732 // (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2), agc->wbd_inv, agc->wbd_sel);
733 dib7000m_write_word(state, 929, (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2));
738 dib7000m_write_word(state, 88 + i, b[i]);
743 static void dib7000m_update_timf(struct dib7000m_state *state)
745 u32 timf = (dib7000m_read_word(state, 436) << 16) | dib7000m_read_word(state, 437);
746 state->timf = timf * 160 / (state->current_bandwidth / 50);
747 dib7000m_write_word(state, 23, (u16) (timf >> 16));
748 dib7000m_write_word(state, 24, (u16) (timf & 0xffff));
749 dprintk("updated timf_frequency: %d (default: %d)\n", state->timf, state->timf_default);
755 struct dib7000m_state *state = demod->demodulator_priv;
756 u16 cfg_72 = dib7000m_read_word(state, 72);
758 u8 *agc_state = &state->agc_state;
761 switch (state->agc_state) {
764 dib7000m_set_power_mode(state, DIB7000M_POWER_INTERF_ANALOG_AGC);
765 dib7000m_set_adc_state(state, DIBX000_ADC_ON);
767 if (dib7000m_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency/1000)) != 0)
776 if (state->cfg.agc_control)
777 state->cfg.agc_control(&state->demod, 1);
779 dib7000m_write_word(state, 75, 32768);
780 if (!state->current_agc->perform_agc_softsplit) {
782 dib7000m_write_word(state, 103, 1 << 8); /* force 0 split on WBD and restart AGC */
792 dib7000m_restart_agc(state);
796 dib7000m_write_word(state, 72, cfg_72 | (1 << 4)); /* freeze AGC loop */
797 dib7000m_write_word(state, 103, 2 << 9); /* fast split search 0.25kHz */
803 agc_split = (u8)dib7000m_read_word(state, 392); /* store the split value for the next time */
804 dib7000m_write_word(state, 75, dib7000m_read_word(state, 390)); /* set AGC gain start value */
806 dib7000m_write_word(state, 72, cfg_72 & ~(1 << 4)); /* std AGC loop */
807 dib7000m_write_word(state, 103, (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
809 dib7000m_restart_agc(state);
821 if (dib7000m_update_lna(state))
829 dib7000m_agc_soft_split(state);
831 if (state->cfg.agc_control)
832 state->cfg.agc_control(&state->demod, 0);
843 static void dib7000m_set_channel(struct dib7000m_state *state, struct dtv_frontend_properties *ch,
848 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
877 dib7000m_write_word(state, 0, value);
878 dib7000m_write_word(state, 5, (seq << 4));
896 dib7000m_write_word(state, 267 + state->reg_offs, value);
901 dib7000m_write_word(state, 26, (6 << 12) | (6 << 8) | 0x80);
904 dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (1 << 9) | (3 << 5) | (1 << 4) | (0x3));
907 dib7000m_write_word(state, 32, (0 << 4) | 0x3);
910 dib7000m_write_word(state, 33, (0 << 4) | 0x5);
926 state->div_sync_wait = (value * 3) / 2 + 32; // add 50% SFN margin + compensate for one DVSY-fifo TODO
930 if (1 == 1 || state->revision > 0x4000)
931 state->div_force_off = 0;
933 state->div_force_off = 1;
934 dib7000m_set_diversity_in(&state->demod, state->div_state);
958 dib7000m_write_word(state, 214 + value + state->reg_offs, est[value]);
961 dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD);
967 struct dib7000m_state *state = demod->demodulator_priv;
981 dib7000m_set_channel(state, &schan, 7);
990 value = 30 * state->internal_clk * factor;
991 ret |= dib7000m_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time
992 ret |= dib7000m_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time
993 value = 100 * state->internal_clk * factor;
994 ret |= dib7000m_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time
995 ret |= dib7000m_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time
996 value = 500 * state->internal_clk * factor;
997 ret |= dib7000m_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time
998 ret |= dib7000m_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time
1001 value = dib7000m_read_word(state, 0);
1002 ret |= dib7000m_write_word(state, 0, (u16) (value | (1 << 9)));
1005 if (state->revision == 0x4000)
1006 dib7000m_write_word(state, 1793, 0);
1008 dib7000m_read_word(state, 537);
1010 ret |= dib7000m_write_word(state, 0, (u16) value);
1015 static int dib7000m_autosearch_irq(struct dib7000m_state *state, u16 reg)
1017 u16 irq_pending = dib7000m_read_word(state, reg);
1033 struct dib7000m_state *state = demod->demodulator_priv;
1034 if (state->revision == 0x4000)
1035 return dib7000m_autosearch_irq(state, 1793);
1037 return dib7000m_autosearch_irq(state, 537);
1043 struct dib7000m_state *state = demod->demodulator_priv;
1048 dib7000m_set_channel(state, ch, 0);
1051 ret |= dib7000m_write_word(state, 898, 0x4000);
1052 ret |= dib7000m_write_word(state, 898, 0x0000);
1055 dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD);
1057 ret |= dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3));
1060 if (state->timf == 0)
1063 //dump_reg(state);
1072 ret |= dib7000m_write_word(state, 26, value);
1082 ret |= dib7000m_write_word(state, 32, value);
1092 ret |= dib7000m_write_word(state, 33, value);
1095 if ((dib7000m_read_word(state, 535) >> 6) & 0x1)
1096 dib7000m_update_timf(state);
1098 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
1104 struct dib7000m_state *state = demod->demodulator_priv;
1106 dib7000m_set_power_mode(state, DIB7000M_POWER_ALL);
1108 if (dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
1123 static int dib7000m_identify(struct dib7000m_state *state)
1127 if ((value = dib7000m_read_word(state, 896)) != 0x01b3) {
1132 state->revision = dib7000m_read_word(state, 897);
1133 if (state->revision != 0x4000 &&
1134 state->revision != 0x4001 &&
1135 state->revision != 0x4002 &&
1136 state->revision != 0x4003) {
1142 if (state->revision == 0x4000 && dib7000m_read_word(state, 769) == 0x4000) {
1147 switch (state->revision) {
1149 case 0x4001: state->reg_offs = 1; dprintk("found DiB7000HC\n"); break;
1150 case 0x4002: state->reg_offs = 1; dprintk("found DiB7000MC\n"); break;
1151 case 0x4003: state->reg_offs = 1; dprintk("found DiB9000\n"); break;
1161 struct dib7000m_state *state = fe->demodulator_priv;
1162 u16 tps = dib7000m_read_word(state,480);
1166 fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth);
1211 /* native interleaver: (dib7000m_read_word(state, 481) >> 5) & 0x1 */
1219 struct dib7000m_state *state = fe->demodulator_priv;
1222 dib7000m_set_output_mode(state, OUTMODE_HIGH_Z);
1224 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz));
1230 state->agc_state = 0;
1259 dib7000m_set_output_mode(state, OUTMODE_MPEG2_FIFO);
1265 struct dib7000m_state *state = fe->demodulator_priv;
1266 u16 lock = dib7000m_read_word(state, 535);
1286 struct dib7000m_state *state = fe->demodulator_priv;
1287 *ber = (dib7000m_read_word(state, 526) << 16) | dib7000m_read_word(state, 527);
1293 struct dib7000m_state *state = fe->demodulator_priv;
1294 *unc = dib7000m_read_word(state, 534);
1300 struct dib7000m_state *state = fe->demodulator_priv;
1301 u16 val = dib7000m_read_word(state, 390);
1334 struct dib7000m_state *state = fe->demodulator_priv;
1335 u16 val = dib7000m_read_word(state, 294 + state->reg_offs) & 0xffef;
1338 return dib7000m_write_word(state, 294 + state->reg_offs, val);
1344 struct dib7000m_state *state = fe->demodulator_priv;
1346 return dib7000m_write_word(state, 300 + state->reg_offs + id,