Lines Matching refs:wr
148 wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
153 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
157 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
169 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
173 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
177 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
181 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
193 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
200 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
209 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
213 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
217 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
230 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
234 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
238 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
248 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
249 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
252 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
253 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
259 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
263 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
267 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
271 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
275 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
294 wr(DIB3000MB_REG_SEQ, seq);
296 wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
300 wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8);
302 wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT);
305 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K);
307 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT);
310 wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF);
311 wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
312 wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF);
316 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE);
318 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL);
319 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
335 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
337 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH);
338 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
357 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL);
358 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
369 wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP);
371 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
373 wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE);
374 wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST);
376 wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT);
378 wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON);
380 wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB);
381 wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB);
390 wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT);
398 wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT);
399 wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
400 wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT);
401 wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
405 wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68);
406 wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69);
407 wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71);
408 wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77);
409 wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78);
410 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
411 wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92);
412 wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96);
413 wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97);
414 wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106);
415 wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107);
416 wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108);
417 wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122);
418 wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
419 wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT);
423 wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON);
424 wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB);
425 wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB);
427 wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE);
429 wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142);
430 wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188);
431 wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
432 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
433 wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146);
434 wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147);
436 wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF);
674 wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN);
705 wr(index+DIB3000MB_REG_FIRST_PID,pid);
715 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);
717 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
726 wr(DIB3000MB_REG_PID_PARSE,onoff);
734 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
736 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));