Lines Matching refs:state

69 static u16 dib0070_read_reg(struct dib0070_state *state, u8 reg)
73 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
78 state->i2c_write_buffer[0] = reg;
80 memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
81 state->msg[0].addr = state->cfg->i2c_address;
82 state->msg[0].flags = 0;
83 state->msg[0].buf = state->i2c_write_buffer;
84 state->msg[0].len = 1;
85 state->msg[1].addr = state->cfg->i2c_address;
86 state->msg[1].flags = I2C_M_RD;
87 state->msg[1].buf = state->i2c_read_buffer;
88 state->msg[1].len = 2;
90 if (i2c_transfer(state->i2c, state->msg, 2) != 2) {
94 ret = (state->i2c_read_buffer[0] << 8)
95 | state->i2c_read_buffer[1];
97 mutex_unlock(&state->i2c_buffer_lock);
101 static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
105 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
109 state->i2c_write_buffer[0] = reg;
110 state->i2c_write_buffer[1] = val >> 8;
111 state->i2c_write_buffer[2] = val & 0xff;
113 memset(state->msg, 0, sizeof(struct i2c_msg));
114 state->msg[0].addr = state->cfg->i2c_address;
115 state->msg[0].flags = 0;
116 state->msg[0].buf = state->i2c_write_buffer;
117 state->msg[0].len = 3;
119 if (i2c_transfer(state->i2c, state->msg, 1) != 1) {
125 mutex_unlock(&state->i2c_buffer_lock);
129 #define HARD_RESET(state) do { \
130 state->cfg->sleep(state->fe, 0); \
131 if (state->cfg->reset) { \
132 state->cfg->reset(state->fe,1); msleep(10); \
133 state->cfg->reset(state->fe,0); msleep(10); \
139 struct dib0070_state *state = fe->tuner_priv;
140 u16 tmp = dib0070_read_reg(state, 0x02) & 0x3fff;
142 if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 7000)
144 else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 6000)
146 else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 5000)
151 dib0070_write_reg(state, 0x02, tmp);
154 if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) {
155 u16 value = dib0070_read_reg(state, 0x17);
157 dib0070_write_reg(state, 0x17, value & 0xfffc);
158 tmp = dib0070_read_reg(state, 0x01) & 0x01ff;
159 dib0070_write_reg(state, 0x01, tmp | (60 << 9));
161 dib0070_write_reg(state, 0x17, value);
166 static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state *tune_state)
173 dib0070_write_reg(state, 0x0f, 0xed10);
174 dib0070_write_reg(state, 0x17, 0x0034);
176 dib0070_write_reg(state, 0x18, 0x0032);
177 state->step = state->captrim = state->fcaptrim = 64;
178 state->adc_diff = 3000;
183 state->step /= 2;
184 dib0070_write_reg(state, 0x14, state->lo4 | state->captrim);
190 adc = dib0070_read_reg(state, 0x19);
192 dprintk("CAPTRIM=%d; ADC = %hd (ADC) & %dmV\n", state->captrim,
203 if (adc < state->adc_diff) {
205 state->captrim, adc, state->adc_diff);
206 state->adc_diff = adc;
207 state->fcaptrim = state->captrim;
209 state->captrim += (step_sign * state->step);
211 if (state->step >= 1)
217 dib0070_write_reg(state, 0x14, state->lo4 | state->fcaptrim);
218 dib0070_write_reg(state, 0x18, 0x07ff);
227 struct dib0070_state *state = fe->tuner_priv;
231 return dib0070_write_reg(state, 0x15, lo5);
236 struct dib0070_state *state = fe->tuner_priv;
239 dib0070_write_reg(state, 0x1b, 0xff00);
240 dib0070_write_reg(state, 0x1a, 0x0000);
242 dib0070_write_reg(state, 0x1b, 0x4112);
243 if (state->cfg->vga_filter != 0) {
244 dib0070_write_reg(state, 0x1a, state->cfg->vga_filter);
245 dprintk("vga filter register is set to %x\n", state->cfg->vga_filter);
247 dib0070_write_reg(state, 0x1a, 0x0009);
323 struct dib0070_state *state = fe->tuner_priv;
328 enum frontend_tune_state *tune_state = &state->tune_state;
332 u32 freq = fe->dtv_property_cache.frequency/1000 + (band == BAND_VHF ? state->cfg->freq_offset_khz_vhf : state->cfg->freq_offset_khz_uhf);
335 if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1)
336 if (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2)
337 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
338 || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
339 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2)))
340 || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
341 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))))
344 if (state->current_rf != freq) {
346 switch (state->revision) {
353 if (state->cfg->flip_chip)
364 state->current_tune_table_index = tune;
365 state->lna_match = lna_match;
370 if (state->current_rf != freq) {
375 state->current_rf = freq;
376 state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7);
379 dib0070_write_reg(state, 0x17, 0x30);
382 VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2;
386 REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000);
389 REFDIV = (u8) ((state->cfg->clock_khz) / 1000);
392 REFDIV = (u8) (state->cfg->clock_khz / 10000);
395 FREF = state->cfg->clock_khz / REFDIV;
399 switch (state->revision) {
401 FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF);
402 Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF;
426 state->lo4 |= (1 << 14) | (1 << 12);
431 dib0070_write_reg(state, 0x11, (u16)FBDiv);
432 dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV);
433 dib0070_write_reg(state, 0x13, (u16) Rest);
435 if (state->revision == DIB0070S_P1A) {
439 dib0070_write_reg(state, 0x1d, 0xFFFF);
444 dib0070_write_reg(state, 0x20,
445 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable);
450 (state->lo4 >> 12) & 0x1);
452 state->current_tune_table_index->hfdiv);
454 state->current_tune_table_index->vco_band);
456 state->current_tune_table_index->vco_multi,
466 ret = dib0070_captrim(state, tune_state);
469 const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
473 dib0070_write_reg(state, 0x0f,
476 | (state->current_tune_table_index->wbdmux << 0));
477 state->wbd_gain_current = tmp->wbd_gain_val;
479 dib0070_write_reg(state, 0x0f,
482 | (state->current_tune_table_index->wbdmux << 0));
483 state->wbd_gain_current = 6;
486 dib0070_write_reg(state, 0x06, 0x3fff);
487 dib0070_write_reg(state, 0x07,
488 (state->current_tune_table_index->switch_trim << 11) | (7 << 8) | (state->lna_match->lna_band << 3) | (3 << 0));
489 dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127));
490 dib0070_write_reg(state, 0x0d, 0x0d80);
493 dib0070_write_reg(state, 0x18, 0x07ff);
494 dib0070_write_reg(state, 0x17, 0x0033);
510 struct dib0070_state *state = fe->tuner_priv;
513 state->tune_state = CT_TUNER_START;
521 } while (state->tune_state != CT_TUNER_STOP);
528 struct dib0070_state *state = fe->tuner_priv;
529 if (state->cfg->sleep)
530 state->cfg->sleep(fe, 0);
536 struct dib0070_state *state = fe->tuner_priv;
537 if (state->cfg->sleep)
538 state->cfg->sleep(fe, 1);
544 struct dib0070_state *state = fe->tuner_priv;
545 return (dib0070_read_reg(state, 0x07) >> 11) & 0x3;
551 struct dib0070_state *state = fe->tuner_priv;
552 u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff;
557 return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11));
600 static u16 dib0070_read_wbd_offset(struct dib0070_state *state, u8 gain)
602 u16 tuner_en = dib0070_read_reg(state, 0x20);
605 dib0070_write_reg(state, 0x18, 0x07ff);
606 dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001);
607 dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0));
609 offset = dib0070_read_reg(state, 0x19);
610 dib0070_write_reg(state, 0x20, tuner_en);
614 static void dib0070_wbd_offset_calibration(struct dib0070_state *state)
618 state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2);
619 dprintk("Gain: %d, WBDOffset (3.3V) = %hd\n", gain, state->wbd_offset_3_3[gain-6]);
625 struct dib0070_state *state = fe->tuner_priv;
626 const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
632 state->wbd_gain_current = tmp->wbd_gain_val;
634 state->wbd_gain_current = 6;
636 return state->wbd_offset_3_3[state->wbd_gain_current - 6];
643 struct dib0070_state *state = fe->tuner_priv;
646 HARD_RESET(state);
650 if ((dib0070_read_reg(state, 0x22) >> 9) & 0x1)
651 state->revision = (dib0070_read_reg(state, 0x1f) >> 8) & 0xff;
656 state->revision = DIB0070S_P1A;
659 dprintk("Revision: %x\n", state->revision);
661 if (state->revision == DIB0070_P1D) {
671 dib0070_write_reg(state, (u8)r, pgm_read_word(n++));
677 if (state->cfg->force_crystal_mode != 0)
678 r = state->cfg->force_crystal_mode;
679 else if (state->cfg->clock_khz >= 24000)
685 r |= state->cfg->osc_buffer_state << 3;
687 dib0070_write_reg(state, 0x10, r);
688 dib0070_write_reg(state, 0x1f, (1 << 8) | ((state->cfg->clock_pad_drive & 0xf) << 5));
690 if (state->cfg->invert_iq) {
691 r = dib0070_read_reg(state, 0x02) & 0xffdf;
692 dib0070_write_reg(state, 0x02, r | (1 << 5));
695 if (state->revision == DIB0070S_P1A)
698 dib0070_set_ctrl_lo5(fe, 5, 4, state->cfg->charge_pump,
699 state->cfg->enable_third_order_filter);
701 dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8);
703 dib0070_wbd_offset_calibration(state);
710 struct dib0070_state *state = fe->tuner_priv;
712 *frequency = 1000 * state->current_rf;
741 struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL);
742 if (state == NULL)
745 state->cfg = cfg;
746 state->i2c = i2c;
747 state->fe = fe;
748 mutex_init(&state->i2c_buffer_lock);
749 fe->tuner_priv = state;
757 fe->tuner_priv = state;
761 kfree(state);