Lines Matching refs:ret
49 int ret;
63 ret = slvt_freeze_reg(tnrdmd);
64 if (ret)
65 return ret;
67 ret = tnrdmd->io->write_reg(tnrdmd->io,
70 if (ret) {
72 return ret;
75 ret = tnrdmd->io->read_regs(tnrdmd->io,
78 if (ret) {
80 return ret;
88 ret = tnrdmd->io->read_regs(tnrdmd->io,
91 if (ret) {
93 return ret;
98 ret = tnrdmd->io->read_regs(tnrdmd->io,
101 if (ret) {
103 return ret;
121 int ret;
135 ret = slvt_freeze_reg(tnrdmd);
136 if (ret)
137 return ret;
139 ret = tnrdmd->io->write_reg(tnrdmd->io,
142 if (ret) {
144 return ret;
147 ret = tnrdmd->io->read_regs(tnrdmd->io,
150 if (ret) {
152 return ret;
162 ret = tnrdmd->io->read_regs(tnrdmd->io,
165 if (ret) {
167 return ret;
177 ret = tnrdmd->io->write_reg(tnrdmd->io,
180 if (ret)
181 return ret;
183 ret = tnrdmd->io->read_regs(tnrdmd->io,
186 if (ret)
187 return ret;
203 int ret;
217 ret = tnrdmd->io->write_reg(tnrdmd->io,
220 if (ret)
221 return ret;
223 ret = tnrdmd->io->read_regs(tnrdmd->io,
226 if (ret)
227 return ret;
234 ret = tnrdmd->io->write_reg(tnrdmd->io,
237 if (ret)
238 return ret;
240 ret = tnrdmd->io->read_regs(tnrdmd->io,
243 if (ret)
244 return ret;
267 int ret;
285 ret = slvt_freeze_reg(tnrdmd);
286 if (ret)
287 return ret;
289 ret = tnrdmd->io->write_reg(tnrdmd->io,
292 if (ret) {
294 return ret;
297 ret = tnrdmd->io->read_regs(tnrdmd->io,
300 if (ret) {
302 return ret;
313 ret = tnrdmd->io->read_regs(tnrdmd->io,
316 if (ret) {
318 return ret;
324 ret = tnrdmd->io->read_regs(tnrdmd->io,
327 if (ret) {
329 return ret;
336 ret = tnrdmd->io->write_reg(tnrdmd->io,
339 if (ret)
340 return ret;
342 ret = tnrdmd->io->read_regs(tnrdmd->io,
345 if (ret)
346 return ret;
369 int ret;
383 ret = tnrdmd->io->write_reg(tnrdmd->io,
386 if (ret)
387 return ret;
389 ret = tnrdmd->io->read_regs(tnrdmd->io,
392 if (ret)
393 return ret;
400 ret = tnrdmd->io->write_reg(tnrdmd->io,
403 if (ret)
404 return ret;
406 ret = tnrdmd->io->read_regs(tnrdmd->io,
409 if (ret)
410 return ret;
425 int ret;
438 ret = tnrdmd->io->write_reg(tnrdmd->io,
441 if (ret)
442 return ret;
444 ret = tnrdmd->io->read_regs(tnrdmd->io,
447 if (ret)
448 return ret;
455 ret = tnrdmd->io->write_reg(tnrdmd->io,
458 if (ret)
459 return ret;
461 ret = tnrdmd->io->read_regs(tnrdmd->io,
464 if (ret)
465 return ret;
489 int ret;
509 ret = cxd2880_tnrdmd_create(&priv->tnrdmd,
511 if (ret) {
513 pr_info("cxd2880 tnrdmd create failed %d\n", ret);
514 return ret;
517 ret = cxd2880_integ_init(&priv->tnrdmd);
518 if (ret) {
520 pr_err("cxd2880 integ init failed %d\n", ret);
521 return ret;
524 ret = cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
527 if (ret) {
529 pr_err("cxd2880 set config failed %d\n", ret);
530 return ret;
536 return ret;
541 int ret;
552 ret = cxd2880_tnrdmd_sleep(&priv->tnrdmd);
555 pr_debug("tnrdmd_sleep ret %d\n", ret);
557 return ret;
563 int ret;
579 ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &level);
597 if (ret)
598 pr_debug("ret = %d\n", ret);
600 return ret;
605 int ret;
620 ret = cxd2880_tnrdmd_dvbt_mon_snr(&priv->tnrdmd,
623 ret = cxd2880_tnrdmd_dvbt2_mon_snr(&priv->tnrdmd,
636 if (ret)
637 pr_debug("ret = %d\n", ret);
639 return ret;
644 int ret;
658 ret = cxd2880_tnrdmd_dvbt_mon_packet_error_number(&priv->tnrdmd,
661 ret = cxd2880_tnrdmd_dvbt2_mon_packet_error_number(&priv->tnrdmd,
670 if (ret)
671 pr_debug("ret = %d\n", ret);
673 return ret;
685 int ret;
704 ret = cxd2880_tnrdmd_dvbt_mon_tps_info(&priv->tnrdmd,
706 if (ret) {
707 pr_err("tps monitor error ret = %d\n", ret);
730 ret = tnrdmd->io->write_reg(tnrdmd->io,
733 if (!ret) {
734 ret = tnrdmd->io->read_regs(tnrdmd->io,
737 if (ret)
796 int ret;
826 ret = cxd2880_tnrdmd_dvbt2_mon_l1_pre(&priv->tnrdmd, &l1pre);
827 if (ret) {
832 ret = cxd2880_tnrdmd_dvbt2_mon_active_plp(&priv->tnrdmd,
834 if (ret) {
839 ret = cxd2880_tnrdmd_dvbt2_mon_l1_post(&priv->tnrdmd, &l1post);
840 if (ret) {
905 ret = cxd2880_tnrdmd_dvbt2_mon_bbheader(&priv->tnrdmd,
908 if (ret) {
963 int ret;
984 ret = cxd2880_tnrdmd_dvbt_tune1(tnr_dmd, tune_param);
985 if (ret)
986 return ret;
998 int ret;
1024 ret = cxd2880_tnrdmd_dvbt2_tune1(tnr_dmd, tune_param);
1025 if (ret)
1026 return ret;
1036 int ret;
1098 ret = cxd2880_dvbt_tune(&priv->tnrdmd,
1106 ret = cxd2880_dvbt2_tune(&priv->tnrdmd,
1115 pr_info("tune result %d\n", ret);
1117 return ret;
1128 int ret;
1160 ret = cxd2880_pre_bit_err_t(&priv->tnrdmd,
1166 ret = cxd2880_pre_bit_err_t2(&priv->tnrdmd,
1174 if (!ret) {
1186 pr_debug("pre_bit_error_t failed %d\n", ret);
1195 ret = cxd2880_post_bit_err_t(&priv->tnrdmd,
1201 ret = cxd2880_post_bit_err_t2(&priv->tnrdmd,
1209 if (!ret) {
1223 pr_debug("post_bit_err_t %d\n", ret);
1232 ret = cxd2880_read_block_err_t(&priv->tnrdmd,
1238 ret = cxd2880_read_block_err_t2(&priv->tnrdmd,
1245 if (!ret) {
1257 pr_debug("read_block_err_t %d\n", ret);
1268 int ret;
1278 ret = cxd2880_tnrdmd_dvbt2_check_l1post_valid(&priv->tnrdmd,
1280 if (ret)
1281 return ret;
1286 ret = cxd2880_tnrdmd_dvbt2_mon_data_plp_error(&priv->tnrdmd,
1288 if (ret)
1289 return ret;
1305 int ret;
1324 ret = cxd2880_tnrdmd_dvbt_mon_sync_stat(&priv->tnrdmd,
1329 ret = cxd2880_tnrdmd_dvbt2_mon_sync_stat(&priv->tnrdmd,
1340 if (ret) {
1342 return ret;
1361 ret = cxd2880_set_ber_per_period_t(fe);
1364 ret = cxd2880_check_l1post_plp(fe);
1365 if (!ret) {
1366 ret = cxd2880_set_ber_per_period_t2(fe);
1387 int ret;
1395 ret = cxd2880_set_frontend(fe);
1396 if (ret) {
1397 pr_err("cxd2880_set_frontend failed %d\n", ret);
1398 return ret;
1410 int ret;
1427 ret = cxd2880_tnrdmd_dvbt_mon_mode_guard(&priv->tnrdmd,
1430 if (!ret) {
1465 pr_debug("ModeGuard err %d\n", ret);
1469 ret = cxd2880_tnrdmd_dvbt_mon_tps_info(&priv->tnrdmd, &tps);
1471 if (!ret) {
1557 pr_debug("TPS info err %d\n", ret);
1561 ret = cxd2880_tnrdmd_dvbt_mon_spectrum_sense(&priv->tnrdmd, &sense);
1563 if (!ret) {
1578 pr_debug("spectrum_sense %d\n", ret);
1582 ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &strength);
1584 if (!ret) {
1591 pr_debug("mon_rf_lvl %d\n", ret);
1594 ret = cxd2880_read_snr(fe, &snr);
1595 if (!ret) {
1602 pr_debug("read_snr %d\n", ret);
1611 int ret;
1628 ret = cxd2880_tnrdmd_dvbt2_mon_l1_pre(&priv->tnrdmd, &l1pre);
1630 if (!ret) {
1687 pr_debug("L1Pre err %d\n", ret);
1691 ret = cxd2880_tnrdmd_dvbt2_mon_code_rate(&priv->tnrdmd,
1695 if (!ret) {
1722 pr_debug("CodeRate %d\n", ret);
1726 ret = cxd2880_tnrdmd_dvbt2_mon_qam(&priv->tnrdmd,
1730 if (!ret) {
1751 pr_debug("QAM %d\n", ret);
1755 ret = cxd2880_tnrdmd_dvbt2_mon_spectrum_sense(&priv->tnrdmd, &sense);
1757 if (!ret) {
1772 pr_debug("SpectrumSense %d\n", ret);
1776 ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &strength);
1778 if (!ret) {
1785 pr_debug("mon_rf_lvl %d\n", ret);
1788 ret = cxd2880_read_snr(fe, &snr);
1789 if (!ret) {
1796 pr_debug("read_snr %d\n", ret);
1805 int ret;
1815 ret = cxd2880_get_frontend_t(fe, props);
1818 ret = cxd2880_get_frontend_t2(fe, props);
1821 ret = -EINVAL;
1825 return ret;
1879 int ret;
1901 ret = cxd2880_spi_device_initialize(&priv->spi_device,
1904 if (ret) {
1905 pr_err("spi_device_initialize failed. %d\n", ret);
1910 ret = cxd2880_spi_device_create_spi(&priv->cxd2880_spi,
1912 if (ret) {
1913 pr_err("spi_device_create_spi failed. %d\n", ret);
1918 ret = cxd2880_io_spi_create(&priv->regio, &priv->cxd2880_spi, 0);
1919 if (ret) {
1920 pr_err("io_spi_create failed. %d\n", ret);
1924 ret = priv->regio.write_reg(&priv->regio,
1926 if (ret) {
1931 ret = priv->regio.read_regs(&priv->regio,
1933 if (ret) {