Lines Matching defs:tnrdmd
28 struct cxd2880_tnrdmd tnrdmd;
45 static int cxd2880_pre_bit_err_t(struct cxd2880_tnrdmd *tnrdmd,
51 if (!tnrdmd || !pre_bit_err || !pre_bit_count)
54 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
57 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
60 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
63 ret = slvt_freeze_reg(tnrdmd);
67 ret = tnrdmd->io->write_reg(tnrdmd->io,
71 slvt_unfreeze_reg(tnrdmd);
75 ret = tnrdmd->io->read_regs(tnrdmd->io,
79 slvt_unfreeze_reg(tnrdmd);
84 slvt_unfreeze_reg(tnrdmd);
88 ret = tnrdmd->io->read_regs(tnrdmd->io,
92 slvt_unfreeze_reg(tnrdmd);
98 ret = tnrdmd->io->read_regs(tnrdmd->io,
102 slvt_unfreeze_reg(tnrdmd);
106 slvt_unfreeze_reg(tnrdmd);
114 static int cxd2880_pre_bit_err_t2(struct cxd2880_tnrdmd *tnrdmd,
123 if (!tnrdmd || !pre_bit_err || !pre_bit_count)
126 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
129 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
132 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
135 ret = slvt_freeze_reg(tnrdmd);
139 ret = tnrdmd->io->write_reg(tnrdmd->io,
143 slvt_unfreeze_reg(tnrdmd);
147 ret = tnrdmd->io->read_regs(tnrdmd->io,
151 slvt_unfreeze_reg(tnrdmd);
156 slvt_unfreeze_reg(tnrdmd);
162 ret = tnrdmd->io->read_regs(tnrdmd->io,
166 slvt_unfreeze_reg(tnrdmd);
175 slvt_unfreeze_reg(tnrdmd);
177 ret = tnrdmd->io->write_reg(tnrdmd->io,
183 ret = tnrdmd->io->read_regs(tnrdmd->io,
196 static int cxd2880_post_bit_err_t(struct cxd2880_tnrdmd *tnrdmd,
205 if (!tnrdmd || !post_bit_err || !post_bit_count)
208 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
211 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
214 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
217 ret = tnrdmd->io->write_reg(tnrdmd->io,
223 ret = tnrdmd->io->read_regs(tnrdmd->io,
234 ret = tnrdmd->io->write_reg(tnrdmd->io,
240 ret = tnrdmd->io->read_regs(tnrdmd->io,
256 static int cxd2880_post_bit_err_t2(struct cxd2880_tnrdmd *tnrdmd,
273 if (!tnrdmd || !post_bit_err || !post_bit_count)
276 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
279 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
282 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
285 ret = slvt_freeze_reg(tnrdmd);
289 ret = tnrdmd->io->write_reg(tnrdmd->io,
293 slvt_unfreeze_reg(tnrdmd);
297 ret = tnrdmd->io->read_regs(tnrdmd->io,
301 slvt_unfreeze_reg(tnrdmd);
306 slvt_unfreeze_reg(tnrdmd);
313 ret = tnrdmd->io->read_regs(tnrdmd->io,
317 slvt_unfreeze_reg(tnrdmd);
324 ret = tnrdmd->io->read_regs(tnrdmd->io,
328 slvt_unfreeze_reg(tnrdmd);
334 slvt_unfreeze_reg(tnrdmd);
336 ret = tnrdmd->io->write_reg(tnrdmd->io,
342 ret = tnrdmd->io->read_regs(tnrdmd->io,
364 static int cxd2880_read_block_err_t(struct cxd2880_tnrdmd *tnrdmd,
371 if (!tnrdmd || !block_err || !block_count)
374 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
377 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
380 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
383 ret = tnrdmd->io->write_reg(tnrdmd->io,
389 ret = tnrdmd->io->read_regs(tnrdmd->io,
400 ret = tnrdmd->io->write_reg(tnrdmd->io,
406 ret = tnrdmd->io->read_regs(tnrdmd->io,
420 static int cxd2880_read_block_err_t2(struct cxd2880_tnrdmd *tnrdmd,
427 if (!tnrdmd || !block_err || !block_count)
430 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
433 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
435 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
438 ret = tnrdmd->io->write_reg(tnrdmd->io,
444 ret = tnrdmd->io->read_regs(tnrdmd->io,
455 ret = tnrdmd->io->write_reg(tnrdmd->io,
461 ret = tnrdmd->io->read_regs(tnrdmd->io,
508 if (priv->tnrdmd.io != &priv->regio) {
509 ret = cxd2880_tnrdmd_create(&priv->tnrdmd,
513 pr_info("cxd2880 tnrdmd create failed %d\n", ret);
517 ret = cxd2880_integ_init(&priv->tnrdmd);
524 ret = cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
552 ret = cxd2880_tnrdmd_sleep(&priv->tnrdmd);
579 ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &level);
620 ret = cxd2880_tnrdmd_dvbt_mon_snr(&priv->tnrdmd,
623 ret = cxd2880_tnrdmd_dvbt2_mon_snr(&priv->tnrdmd,
658 ret = cxd2880_tnrdmd_dvbt_mon_packet_error_number(&priv->tnrdmd,
661 ret = cxd2880_tnrdmd_dvbt2_mon_packet_error_number(&priv->tnrdmd,
704 ret = cxd2880_tnrdmd_dvbt_mon_tps_info(&priv->tnrdmd,
728 struct cxd2880_tnrdmd *tnrdmd = &priv->tnrdmd;
730 ret = tnrdmd->io->write_reg(tnrdmd->io,
734 ret = tnrdmd->io->read_regs(tnrdmd->io,
771 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
779 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
787 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
826 ret = cxd2880_tnrdmd_dvbt2_mon_l1_pre(&priv->tnrdmd, &l1pre);
832 ret = cxd2880_tnrdmd_dvbt2_mon_active_plp(&priv->tnrdmd,
839 ret = cxd2880_tnrdmd_dvbt2_mon_l1_post(&priv->tnrdmd, &l1post);
893 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
901 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
905 ret = cxd2880_tnrdmd_dvbt2_mon_bbheader(&priv->tnrdmd,
936 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
944 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
948 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
953 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
1094 priv->tnrdmd.sys = CXD2880_DTV_SYS_DVBT;
1098 ret = cxd2880_dvbt_tune(&priv->tnrdmd,
1101 priv->tnrdmd.sys = CXD2880_DTV_SYS_DVBT2;
1106 ret = cxd2880_dvbt2_tune(&priv->tnrdmd,
1160 ret = cxd2880_pre_bit_err_t(&priv->tnrdmd,
1166 ret = cxd2880_pre_bit_err_t2(&priv->tnrdmd,
1195 ret = cxd2880_post_bit_err_t(&priv->tnrdmd,
1201 ret = cxd2880_post_bit_err_t2(&priv->tnrdmd,
1232 ret = cxd2880_read_block_err_t(&priv->tnrdmd,
1238 ret = cxd2880_read_block_err_t2(&priv->tnrdmd,
1278 ret = cxd2880_tnrdmd_dvbt2_check_l1post_valid(&priv->tnrdmd,
1286 ret = cxd2880_tnrdmd_dvbt2_mon_data_plp_error(&priv->tnrdmd,
1321 if (priv->tnrdmd.state == CXD2880_TNRDMD_STATE_ACTIVE) {
1324 ret = cxd2880_tnrdmd_dvbt_mon_sync_stat(&priv->tnrdmd,
1329 ret = cxd2880_tnrdmd_dvbt2_mon_sync_stat(&priv->tnrdmd,
1341 pr_err("failed. sys = %d\n", priv->tnrdmd.sys);
1427 ret = cxd2880_tnrdmd_dvbt_mon_mode_guard(&priv->tnrdmd,
1469 ret = cxd2880_tnrdmd_dvbt_mon_tps_info(&priv->tnrdmd, &tps);
1561 ret = cxd2880_tnrdmd_dvbt_mon_spectrum_sense(&priv->tnrdmd, &sense);
1582 ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &strength);
1628 ret = cxd2880_tnrdmd_dvbt2_mon_l1_pre(&priv->tnrdmd, &l1pre);
1691 ret = cxd2880_tnrdmd_dvbt2_mon_code_rate(&priv->tnrdmd,
1726 ret = cxd2880_tnrdmd_dvbt2_mon_qam(&priv->tnrdmd,
1755 ret = cxd2880_tnrdmd_dvbt2_mon_spectrum_sense(&priv->tnrdmd, &sense);
1776 ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &strength);