Lines Matching defs:cx24123_readreg
274 #define cx24123_readreg(state, reg) \
282 u8 nom_reg = cx24123_readreg(state, 0x0e);
283 u8 auto_reg = cx24123_readreg(state, 0x10);
312 val = cx24123_readreg(state, 0x1b) >> 7;
327 u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07;
335 cx24123_readreg(state, 0x43) | 0x01);
338 cx24123_readreg(state, 0x43) & ~0x01);
391 ret = cx24123_readreg(state, 0x1b);
488 tmp = cx24123_readreg(state, 0x0c) & ~0xe0;
593 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
605 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
618 while ((cx24123_readreg(state, 0x20) & 0x80)) {
628 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2);
629 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd);
656 val = cx24123_readreg(state, 0x28) & ~0x3;
678 u8 r = cx24123_readreg(state, 0x23) & 0x1e;
701 cx24123_readreg(state, 0x32) | 0x02);
715 val = cx24123_readreg(state, 0x29) & ~0x40;
738 while (!(cx24123_readreg(state, 0x29) & 0x40)) {
757 tone = cx24123_readreg(state, 0x29);
765 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
770 val = cx24123_readreg(state, 0x29);
793 tone = cx24123_readreg(state, 0x29);
801 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4);
803 val = cx24123_readreg(state, 0x29);
812 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
824 int sync = cx24123_readreg(state, 0x14);
834 int lock = cx24123_readreg(state, 0x20);
864 *ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) |
865 (cx24123_readreg(state, 0x1d) << 8 |
866 cx24123_readreg(state, 0x1e));
879 *signal_strength = cx24123_readreg(state, 0x3b) << 8;
892 *snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) |
893 (u16)cx24123_readreg(state, 0x19));
925 cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
964 val = cx24123_readreg(state, 0x29) & ~0x40;
1059 state->demod_rev = cx24123_readreg(state, 0x00);