Lines Matching refs:state

90 static int cx24113_writereg(struct cx24113_state *state, int reg, int data)
93 struct i2c_msg msg = { .addr = state->config->i2c_addr,
95 int err = i2c_transfer(state->i2c, &msg, 1);
105 static int cx24113_readreg(struct cx24113_state *state, u8 reg)
110 { .addr = state->config->i2c_addr,
112 { .addr = state->config->i2c_addr,
116 ret = i2c_transfer(state->i2c, msg, 2);
127 static void cx24113_set_parameters(struct cx24113_state *state)
131 r = cx24113_readreg(state, 0x10) & 0x82;
132 r |= state->icp_mode;
133 r |= state->icp_man << 4;
134 r |= state->icp_dig << 2;
135 r |= state->prescaler_mode << 5;
136 cx24113_writereg(state, 0x10, r);
138 r = (state->icp_auto_low << 0) | (state->icp_auto_mlow << 2)
139 | (state->icp_auto_mhi << 4) | (state->icp_auto_hi << 6);
140 cx24113_writereg(state, 0x11, r);
142 if (state->rev == REV_CX24113) {
143 r = cx24113_readreg(state, 0x20) & 0xec;
144 r |= state->lna_gain;
145 r |= state->rfvga_bias_ctrl << 4;
146 cx24113_writereg(state, 0x20, r);
149 r = cx24113_readreg(state, 0x12) & 0x03;
150 r |= state->acp_on << 2;
151 r |= state->bs_delay << 4;
152 cx24113_writereg(state, 0x12, r);
154 r = cx24113_readreg(state, 0x18) & 0x40;
155 r |= state->vco_shift;
156 if (state->vco_band == VCOBANDSEL_6)
159 r |= (state->vco_band << 1);
160 cx24113_writereg(state, 0x18, r);
162 r = cx24113_readreg(state, 0x14) & 0x20;
163 r |= (state->vco_mode << 6) | ((state->bs_freqcnt >> 8) & 0x1f);
164 cx24113_writereg(state, 0x14, r);
165 cx24113_writereg(state, 0x15, (state->bs_freqcnt & 0xff));
167 cx24113_writereg(state, 0x16, (state->bs_rdiv >> 4) & 0xff);
168 r = (cx24113_readreg(state, 0x17) & 0x0f) |
169 ((state->bs_rdiv & 0x0f) << 4);
170 cx24113_writereg(state, 0x17, r);
187 static int cx24113_set_gain_settings(struct cx24113_state *state,
190 u8 ampout = cx24113_readreg(state, 0x1d) & 0xf0,
191 vga = cx24113_readreg(state, 0x1f) & 0x3f,
192 rfvga = cx24113_readreg(state, 0x20) & 0xf3;
193 u8 gain_level = power_estimation >= state->tuner_gain_thres;
196 power_estimation, state->tuner_gain_thres,
197 state->gain_level, gain_level);
199 if (gain_level == state->gain_level)
211 state->gain_level = gain_level;
213 cx24113_writereg(state, 0x1d, ampout);
214 cx24113_writereg(state, 0x1f, vga);
215 cx24113_writereg(state, 0x20, rfvga);
220 static int cx24113_set_Fref(struct cx24113_state *state, u8 high)
222 u8 xtal = cx24113_readreg(state, 0x02);
223 if (state->rev == 0x43 && state->vcodiv == VCODIV4)
229 return cx24113_writereg(state, 0x02, xtal);
232 static int cx24113_enable(struct cx24113_state *state, u8 enable)
234 u8 r21 = (cx24113_readreg(state, 0x21) & 0xc0) | enable;
235 if (state->rev == REV_CX24113)
237 return cx24113_writereg(state, 0x21, r21);
240 static int cx24113_set_bandwidth(struct cx24113_state *state, u32 bandwidth_khz)
262 return cx24113_writereg(state, 0x1e, r);
265 static int cx24113_set_clk_inversion(struct cx24113_state *state, u8 on)
267 u8 r = (cx24113_readreg(state, 0x10) & 0x7f) | ((on & 0x1) << 7);
268 return cx24113_writereg(state, 0x10, r);
273 struct cx24113_state *state = fe->tuner_priv;
274 u8 r = (cx24113_readreg(state, 0x10) & 0x02) >> 1;
281 static u8 cx24113_set_ref_div(struct cx24113_state *state, u8 refdiv)
283 if (state->rev == 0x43 && state->vcodiv == VCODIV4)
285 return state->refdiv = refdiv;
288 static void cx24113_calc_pll_nf(struct cx24113_state *state, u16 *n, s32 *f)
296 s32 freq_hz = state->frequency * 1000;
298 if (state->config->xtal_khz < 20000)
303 if (state->rev == REV_CX24113) {
304 if (state->frequency >= 1100000)
309 if (state->frequency >= 1165000)
314 state->vcodiv = vcodiv;
319 R = cx24113_set_ref_div(state, R + 1);
323 N /= (state->config->xtal_khz) * factor * 2;
338 do_div(dividend, state->config->xtal_khz * 1000 * factor * 2);
345 if (state->Fwindow_enabled) {
352 r = cx24113_readreg(state, 0x10);
353 cx24113_writereg(state, 0x10, r | (1 << 6));
363 static void cx24113_set_nfr(struct cx24113_state *state, u16 n, s32 f, u8 r)
366 cx24113_writereg(state, 0x19, (n >> 1) & 0xff);
369 cx24113_writereg(state, 0x1a, reg);
371 cx24113_writereg(state, 0x1b, (f >> 3) & 0xff);
373 reg = cx24113_readreg(state, 0x1c) & 0x1f;
374 cx24113_writereg(state, 0x1c, reg | ((f & 0x7) << 5));
376 cx24113_set_Fref(state, r - 1);
379 static int cx24113_set_frequency(struct cx24113_state *state, u32 frequency)
385 r = cx24113_readreg(state, 0x14);
386 cx24113_writereg(state, 0x14, r & 0x3f);
388 r = cx24113_readreg(state, 0x10);
389 cx24113_writereg(state, 0x10, r & 0xbf);
391 state->frequency = frequency;
395 cx24113_calc_pll_nf(state, &n, &f);
396 cx24113_set_nfr(state, n, f, state->refdiv);
398 r = cx24113_readreg(state, 0x18) & 0xbf;
399 if (state->vcodiv != VCODIV2)
401 cx24113_writereg(state, 0x18, r);
406 r = cx24113_readreg(state, 0x1c) & 0xef;
407 cx24113_writereg(state, 0x1c, r | (1 << 4));
413 struct cx24113_state *state = fe->tuner_priv;
416 state->tuner_gain_thres = -50;
417 state->gain_level = 255; /* to force a gain-setting initialization */
418 state->icp_mode = 0;
420 if (state->config->xtal_khz < 11000) {
421 state->icp_auto_hi = ICP_LEVEL4;
422 state->icp_auto_mhi = ICP_LEVEL4;
423 state->icp_auto_mlow = ICP_LEVEL3;
424 state->icp_auto_low = ICP_LEVEL3;
426 state->icp_auto_hi = ICP_LEVEL4;
427 state->icp_auto_mhi = ICP_LEVEL4;
428 state->icp_auto_mlow = ICP_LEVEL3;
429 state->icp_auto_low = ICP_LEVEL2;
432 state->icp_dig = ICP_LEVEL3;
433 state->icp_man = ICP_LEVEL1;
434 state->acp_on = 1;
435 state->vco_mode = 0;
436 state->vco_shift = 0;
437 state->vco_band = VCOBANDSEL_1;
438 state->bs_delay = 8;
439 state->bs_freqcnt = 0x0fff;
440 state->bs_rdiv = 0x0fff;
441 state->prescaler_mode = 0;
442 state->lna_gain = LNA_MAX_GAIN;
443 state->rfvga_bias_ctrl = 1;
444 state->Fwindow_enabled = 1;
446 cx24113_set_Fref(state, 0);
447 cx24113_enable(state, 0x3d);
448 cx24113_set_parameters(state);
450 cx24113_set_gain_settings(state, -30);
452 cx24113_set_bandwidth(state, 18025);
453 cx24113_set_clk_inversion(state, 1);
455 if (state->config->xtal_khz >= 40000)
456 ret = cx24113_writereg(state, 0x02,
457 (cx24113_readreg(state, 0x02) & 0xfb) | (1 << 2));
459 ret = cx24113_writereg(state, 0x02,
460 (cx24113_readreg(state, 0x02) & 0xfb) | (0 << 2));
468 struct cx24113_state *state = fe->tuner_priv;
477 cx24113_set_bandwidth(state, bw);
479 cx24113_set_frequency(state, c->frequency);
491 struct cx24113_state *state = fe->tuner_priv;
502 if (cx24113_agc_table[state->gain_level][i] > s)
505 } while (cx24113_set_gain_settings(state, s));
511 struct cx24113_state *state = fe->tuner_priv;
512 *frequency = state->frequency;
518 struct cx24113_state *state = fe->tuner_priv;
521 kfree(state);
544 /* allocate memory for the internal state */
545 struct cx24113_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
548 if (!state)
551 /* setup the state */
552 state->config = config;
553 state->i2c = i2c;
559 cx24113_readreg(state, 0x00);
561 rc = cx24113_readreg(state, 0x00);
566 state->rev = rc;
576 cx_err("unsupported device id: %x\n", state->rev);
579 state->ver = cx24113_readreg(state, 0x01);
580 cx_info("version: %x\n", state->ver);
585 fe->tuner_priv = state;
589 kfree(state);