Lines Matching refs:value
114 static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
117 writel(value, hsp->regs + offset);
127 u32 value, unsigned int offset)
129 writel(value, channel->regs + offset);
134 u32 value;
136 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE);
138 return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0;
170 unsigned long master, value;
176 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING);
177 tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING);
181 for_each_set_bit(master, &value, hsp->mbox_db.num_chans) {
209 u32 status, value;
247 value = tegra_hsp_channel_readl(&mb->channel,
249 value &= ~HSP_SM_SHRD_MBOX_FULL;
250 msg = (void *)(unsigned long)value;
314 u32 value;
337 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
338 value |= BIT(db->master);
339 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
352 u32 value;
360 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
361 value &= ~BIT(db->master);
362 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
378 u32 value;
384 value = (u32)(unsigned long)data;
385 value |= HSP_SM_SHRD_MBOX_FULL;
387 tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX);
405 u32 value;
410 value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX);
411 if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) {
648 u32 value;
665 value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
666 hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
667 hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
668 hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
669 hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
670 hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;