Lines Matching defs:hsp
18 #include <dt-bindings/mailbox/tegra186-hsp.h>
57 struct tegra_hsp *hsp;
109 static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
111 return readl(hsp->regs + offset);
114 static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
117 writel(value, hsp->regs + offset);
142 __tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
146 list_for_each_entry(entry, &hsp->doorbells, list)
154 tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
159 spin_lock_irqsave(&hsp->lock, flags);
160 db = __tegra_hsp_doorbell_get(hsp, master);
161 spin_unlock_irqrestore(&hsp->lock, flags);
168 struct tegra_hsp *hsp = data;
172 db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
179 spin_lock(&hsp->lock);
181 for_each_set_bit(master, &value, hsp->mbox_db.num_chans) {
184 db = __tegra_hsp_doorbell_get(hsp, master);
200 spin_unlock(&hsp->lock);
207 struct tegra_hsp *hsp = data;
212 status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
217 for_each_set_bit(bit, &mask, hsp->num_sm) {
218 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
228 spin_lock(&hsp->lock);
230 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
231 tegra_hsp_writel(hsp, hsp->mask,
232 HSP_INT_IE(hsp->shared_irq));
234 spin_unlock(&hsp->lock);
243 for_each_set_bit(bit, &mask, hsp->num_sm) {
244 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
271 tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
278 db = devm_kzalloc(hsp->dev, sizeof(*db), GFP_KERNEL);
282 offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
285 db->channel.regs = hsp->regs + offset;
286 db->channel.hsp = hsp;
288 db->name = devm_kstrdup_const(hsp->dev, name, GFP_KERNEL);
292 spin_lock_irqsave(&hsp->lock, flags);
293 list_add_tail(&db->list, &hsp->doorbells);
294 spin_unlock_irqrestore(&hsp->lock, flags);
311 struct tegra_hsp *hsp = db->channel.hsp;
323 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
335 spin_lock_irqsave(&hsp->lock, flags);
341 spin_unlock_irqrestore(&hsp->lock, flags);
349 struct tegra_hsp *hsp = db->channel.hsp;
354 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
358 spin_lock_irqsave(&hsp->lock, flags);
364 spin_unlock_irqrestore(&hsp->lock, flags);
376 struct tegra_hsp *hsp = mb->channel.hsp;
390 spin_lock_irqsave(&hsp->lock, flags);
392 hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index);
393 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
395 spin_unlock_irqrestore(&hsp->lock, flags);
431 struct tegra_hsp *hsp = mb->channel.hsp;
447 spin_lock_irqsave(&hsp->lock, flags);
450 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
452 hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index);
454 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
456 spin_unlock_irqrestore(&hsp->lock, flags);
458 if (hsp->soc->has_per_mb_ie) {
474 struct tegra_hsp *hsp = mb->channel.hsp;
477 if (hsp->soc->has_per_mb_ie) {
486 spin_lock_irqsave(&hsp->lock, flags);
489 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
491 hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index);
493 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
495 spin_unlock_irqrestore(&hsp->lock, flags);
508 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db);
516 if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq)
519 db = tegra_hsp_doorbell_get(hsp, master);
526 spin_lock_irqsave(&hsp->lock, flags);
539 spin_unlock_irqrestore(&hsp->lock, flags);
547 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm);
553 if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs ||
554 index >= hsp->num_sm)
557 mb = &hsp->mailboxes[index];
567 static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
569 const struct tegra_hsp_db_map *map = hsp->soc->map;
573 channel = tegra_hsp_doorbell_create(hsp, map->name,
584 static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev)
588 hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes),
590 if (!hsp->mailboxes)
593 for (i = 0; i < hsp->num_sm; i++) {
594 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
598 mb->channel.hsp = hsp;
599 mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K;
600 mb->channel.chan = &hsp->mbox_sm.chans[i];
607 static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp)
612 for (i = 0; i < hsp->num_si; i++) {
613 irq = hsp->shared_irqs[i];
617 err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0,
618 dev_name(hsp->dev), hsp);
620 dev_err(hsp->dev, "failed to request interrupt: %d\n",
625 hsp->shared_irq = i;
628 tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq));
630 dev_dbg(hsp->dev, "interrupt requested: %u\n", irq);
635 if (i == hsp->num_si) {
636 dev_err(hsp->dev, "failed to find available interrupt\n");
645 struct tegra_hsp *hsp;
651 hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
652 if (!hsp)
655 hsp->dev = &pdev->dev;
656 hsp->soc = of_device_get_match_data(&pdev->dev);
657 INIT_LIST_HEAD(&hsp->doorbells);
658 spin_lock_init(&hsp->lock);
661 hsp->regs = devm_ioremap_resource(&pdev->dev, res);
662 if (IS_ERR(hsp->regs))
663 return PTR_ERR(hsp->regs);
665 value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
666 hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
667 hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
668 hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
669 hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
670 hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
674 hsp->doorbell_irq = err;
676 if (hsp->num_si > 0) {
679 hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si,
680 sizeof(*hsp->shared_irqs),
682 if (!hsp->shared_irqs)
685 for (i = 0; i < hsp->num_si; i++) {
694 hsp->shared_irqs[i] = err;
702 devm_kfree(&pdev->dev, hsp->shared_irqs);
703 hsp->shared_irqs = NULL;
708 hsp->mbox_db.of_xlate = tegra_hsp_db_xlate;
709 hsp->mbox_db.num_chans = 32;
710 hsp->mbox_db.dev = &pdev->dev;
711 hsp->mbox_db.ops = &tegra_hsp_db_ops;
713 hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans,
714 sizeof(*hsp->mbox_db.chans),
716 if (!hsp->mbox_db.chans)
719 if (hsp->doorbell_irq) {
720 err = tegra_hsp_add_doorbells(hsp);
728 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_db);
736 hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate;
737 hsp->mbox_sm.num_chans = hsp->num_sm;
738 hsp->mbox_sm.dev = &pdev->dev;
739 hsp->mbox_sm.ops = &tegra_hsp_sm_ops;
741 hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans,
742 sizeof(*hsp->mbox_sm.chans),
744 if (!hsp->mbox_sm.chans)
747 if (hsp->shared_irqs) {
748 err = tegra_hsp_add_mailboxes(hsp, &pdev->dev);
756 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_sm);
763 platform_set_drvdata(pdev, hsp);
765 if (hsp->doorbell_irq) {
766 err = devm_request_irq(&pdev->dev, hsp->doorbell_irq,
768 dev_name(&pdev->dev), hsp);
772 hsp->doorbell_irq, err);
777 if (hsp->shared_irqs) {
778 err = tegra_hsp_request_shared_irq(hsp);
788 struct tegra_hsp *hsp = dev_get_drvdata(dev);
792 list_for_each_entry(db, &hsp->doorbells, list) {
797 if (hsp->mailboxes) {
798 for (i = 0; i < hsp->num_sm; i++) {
799 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
830 { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
831 { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
837 .name = "tegra-hsp",