Lines Matching defs:ipcc
83 struct stm32_ipcc *ipcc = data;
84 struct device *dev = ipcc->controller.dev;
90 proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
91 tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
92 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
97 for (chan = 0; chan < ipcc->n_chans; chan++) {
103 mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);
105 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
116 struct stm32_ipcc *ipcc = data;
117 struct device *dev = ipcc->controller.dev;
121 tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR);
122 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
127 for (chan = 0; chan < ipcc->n_chans ; chan++) {
134 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
137 mbox_chan_txdone(&ipcc->controller.chans[chan], 0);
148 struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
151 dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan);
154 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
158 stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
167 struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
171 ret = clk_prepare_enable(ipcc->clk);
173 dev_err(ipcc->controller.dev, "can not enable the clock\n");
178 stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
187 struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
191 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
194 clk_disable_unprepare(ipcc->clk);
207 struct stm32_ipcc *ipcc;
220 ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL);
221 if (!ipcc)
224 spin_lock_init(&ipcc->lock);
227 if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {
232 if (ipcc->proc_id >= STM32_MAX_PROCS) {
233 dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
239 ipcc->reg_base = devm_ioremap_resource(dev, res);
240 if (IS_ERR(ipcc->reg_base))
241 return PTR_ERR(ipcc->reg_base);
243 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
246 ipcc->clk = devm_clk_get(dev, NULL);
247 if (IS_ERR(ipcc->clk))
248 return PTR_ERR(ipcc->clk);
250 ret = clk_prepare_enable(ipcc->clk);
258 ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]);
259 if (ipcc->irqs[i] < 0) {
260 if (ipcc->irqs[i] != -EPROBE_DEFER)
263 ret = ipcc->irqs[i];
267 ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL,
269 dev_name(dev), ipcc);
277 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
279 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XCR,
286 ret = dev_pm_set_wake_irq(dev, ipcc->irqs[IPCC_IRQ_RX]);
294 ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR);
295 ipcc->n_chans &= IPCFGR_CHAN_MASK;
297 ipcc->controller.dev = dev;
298 ipcc->controller.txdone_irq = true;
299 ipcc->controller.ops = &stm32_ipcc_ops;
300 ipcc->controller.num_chans = ipcc->n_chans;
301 ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans,
302 sizeof(*ipcc->controller.chans),
304 if (!ipcc->controller.chans) {
309 for (i = 0; i < ipcc->controller.num_chans; i++)
310 ipcc->controller.chans[i].con_priv = (void *)i;
312 ret = devm_mbox_controller_register(dev, &ipcc->controller);
316 platform_set_drvdata(pdev, ipcc);
318 ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER);
320 dev_info(dev, "ipcc rev:%ld.%ld enabled, %d chans, proc %d\n",
323 ipcc->controller.num_chans, ipcc->proc_id);
325 clk_disable_unprepare(ipcc->clk);
334 clk_disable_unprepare(ipcc->clk);
353 struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
355 ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
356 ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR);
363 struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
365 writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);
366 writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);
376 { .compatible = "st,stm32mp1-ipcc" },
383 .name = "stm32-ipcc",