Lines Matching defs:pdcs
427 struct pdc_state *pdcs;
437 pdcs = filp->private_data;
440 "SPU %u stats:\n", pdcs->pdc_idx);
443 pdcs->pdc_requests);
446 pdcs->pdc_replies);
449 pdcs->last_tx_not_done);
452 pdcs->tx_ring_full);
455 pdcs->rx_ring_full);
458 pdcs->txnobuf);
461 pdcs->rxnobuf);
464 pdcs->rx_oflow);
467 NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr,
468 pdcs->nrxpost));
488 * @pdcs: PDC state structure
490 static void pdc_setup_debugfs(struct pdc_state *pdcs)
497 snprintf(spu_stats_name, 16, "pdc%d_stats", pdcs->pdc_idx);
502 debugfs_create_file(spu_stats_name, 0400, debugfs_dir, pdcs,
514 * @pdcs: PDC state for SPU that will generate result
520 pdc_build_rxd(struct pdc_state *pdcs, dma_addr_t dma_addr,
523 struct device *dev = &pdcs->pdev->dev;
524 struct dma64dd *rxd = &pdcs->rxd_64[pdcs->rxout];
528 pdcs->pdc_idx, pdcs->rxout, buf_len, flags);
536 pdcs->rxout = NEXTRXD(pdcs->rxout, pdcs->nrxpost);
542 * @pdcs: PDC state for the SPU that will process this request
548 pdc_build_txd(struct pdc_state *pdcs, dma_addr_t dma_addr, u32 buf_len,
551 struct device *dev = &pdcs->pdev->dev;
552 struct dma64dd *txd = &pdcs->txd_64[pdcs->txout];
556 pdcs->pdc_idx, pdcs->txout, buf_len, flags);
564 pdcs->txout = NEXTTXD(pdcs->txout, pdcs->ntxpost);
569 * @pdcs: PDC state for the SPU to receive from
579 pdc_receive_one(struct pdc_state *pdcs)
581 struct device *dev = &pdcs->pdev->dev;
593 mbc = &pdcs->mbc;
602 frags_rdy = NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, pdcs->nrxpost);
604 (frags_rdy < pdcs->rx_ctx[pdcs->rxin].rxin_numd))
608 num_frags = pdcs->txin_numd[pdcs->txin];
611 dma_unmap_sg(dev, pdcs->src_sg[pdcs->txin],
612 sg_nents(pdcs->src_sg[pdcs->txin]), DMA_TO_DEVICE);
614 pdcs->txin = (pdcs->txin + num_frags) & pdcs->ntxpost;
617 pdcs->pdc_idx, num_frags);
619 rx_idx = pdcs->rxin;
620 rx_ctx = &pdcs->rx_ctx[rx_idx];
630 pdcs->rxin = (pdcs->rxin + num_frags) & pdcs->nrxpost;
633 pdcs->pdc_idx, num_frags);
637 pdcs->pdc_idx, pdcs->txin, pdcs->txout, pdcs->rxin,
638 pdcs->rxout, pdcs->last_rx_curr);
640 if (pdcs->pdc_resp_hdr_len == PDC_SPUM_RESP_HDR_LEN) {
652 pdcs->rx_oflow++;
660 dma_pool_free(pdcs->rx_buf_pool, resp_hdr, resp_hdr_daddr);
664 pdcs->pdc_replies++;
670 * @pdcs: PDC state
676 pdc_receive(struct pdc_state *pdcs)
681 pdcs->last_rx_curr =
682 (ioread32((const void __iomem *)&pdcs->rxregs_64->status0) &
687 rx_status = pdc_receive_one(pdcs);
706 static int pdc_tx_list_sg_add(struct pdc_state *pdcs, struct scatterlist *sg)
724 tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout,
725 pdcs->ntxpost);
727 pdcs->txnobuf++;
732 if (pdcs->tx_msg_start == pdcs->txout) {
734 pdcs->txin_numd[pdcs->tx_msg_start] = 0;
735 pdcs->src_sg[pdcs->txout] = sg;
740 if (unlikely(pdcs->txout == (pdcs->ntxd - 1)))
752 pdc_build_txd(pdcs, databufptr, PDC_DMA_BUF_MAX,
757 if (unlikely(pdcs->txout == (pdcs->ntxd - 1)))
766 pdc_build_txd(pdcs, databufptr, bufcnt, flags | eot);
771 pdcs->txin_numd[pdcs->tx_msg_start] += desc_w;
779 * @pdcs: PDC state for SPU to process the request
785 static int pdc_tx_list_final(struct pdc_state *pdcs)
792 iowrite32(pdcs->rxout << 4, &pdcs->rxregs_64->ptr);
793 iowrite32(pdcs->txout << 4, &pdcs->txregs_64->ptr);
794 pdcs->pdc_requests++;
801 * @pdcs: PDC state for SPU handling request
814 static int pdc_rx_list_init(struct pdc_state *pdcs, struct scatterlist *dst_sg,
824 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout,
825 pdcs->nrxpost);
827 pdcs->rxnobuf++;
832 vaddr = dma_pool_zalloc(pdcs->rx_buf_pool, GFP_ATOMIC, &daddr);
841 pdcs->rx_msg_start = pdcs->rxout;
842 pdcs->tx_msg_start = pdcs->txout;
846 pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd = 1;
848 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1)))
851 rx_ctx = &pdcs->rx_ctx[pdcs->rxout];
856 pdc_build_rxd(pdcs, daddr, pdcs->pdc_resp_hdr_len, flags);
874 static int pdc_rx_list_sg_add(struct pdc_state *pdcs, struct scatterlist *sg)
890 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout,
891 pdcs->nrxpost);
893 pdcs->rxnobuf++;
898 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1)))
910 pdc_build_rxd(pdcs, databufptr, PDC_DMA_BUF_MAX, flags);
914 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1)))
919 pdc_build_rxd(pdcs, databufptr, bufcnt, flags);
923 pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd += desc_w;
943 struct pdc_state *pdcs = dev_get_drvdata(dev);
944 u32 intstatus = ioread32(pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET);
950 iowrite32(0, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET);
953 iowrite32(intstatus, pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET);
956 tasklet_schedule(&pdcs->rx_tasklet);
967 struct pdc_state *pdcs = from_tasklet(pdcs, t, rx_tasklet);
969 pdc_receive(pdcs);
972 iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET);
978 * @pdcs: PDC instance state
984 static int pdc_ring_init(struct pdc_state *pdcs, int ringset)
989 struct device *dev = &pdcs->pdev->dev;
994 tx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &tx.dmabase);
1001 rx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &rx.dmabase);
1012 memcpy(&pdcs->tx_ring_alloc, &tx, sizeof(tx));
1013 memcpy(&pdcs->rx_ring_alloc, &rx, sizeof(rx));
1015 pdcs->rxin = 0;
1016 pdcs->rx_msg_start = 0;
1017 pdcs->last_rx_curr = 0;
1018 pdcs->rxout = 0;
1019 pdcs->txin = 0;
1020 pdcs->tx_msg_start = 0;
1021 pdcs->txout = 0;
1024 pdcs->txd_64 = (struct dma64dd *)pdcs->tx_ring_alloc.vbase;
1025 pdcs->rxd_64 = (struct dma64dd *)pdcs->rx_ring_alloc.vbase;
1028 dma_reg = &pdcs->regs->dmaregs[ringset];
1032 iowrite32((PDC_RX_CTL + (pdcs->rx_status_len << 1)),
1038 iowrite32(lower_32_bits(pdcs->tx_ring_alloc.dmabase),
1040 iowrite32(upper_32_bits(pdcs->tx_ring_alloc.dmabase),
1043 iowrite32(lower_32_bits(pdcs->rx_ring_alloc.dmabase),
1045 iowrite32(upper_32_bits(pdcs->rx_ring_alloc.dmabase),
1050 iowrite32((PDC_RX_CTL | PDC_RX_ENABLE | (pdcs->rx_status_len << 1)),
1056 if (i != pdcs->ntxpost) {
1058 &pdcs->txd_64[i].ctrl1);
1062 D64_CTRL1_EOT, &pdcs->txd_64[i].ctrl1);
1066 if (i != pdcs->nrxpost) {
1068 &pdcs->rxd_64[i].ctrl1);
1072 &pdcs->rxd_64[i].ctrl1);
1078 dma_pool_free(pdcs->ring_pool, tx.vbase, tx.dmabase);
1083 static void pdc_ring_free(struct pdc_state *pdcs)
1085 if (pdcs->tx_ring_alloc.vbase) {
1086 dma_pool_free(pdcs->ring_pool, pdcs->tx_ring_alloc.vbase,
1087 pdcs->tx_ring_alloc.dmabase);
1088 pdcs->tx_ring_alloc.vbase = NULL;
1091 if (pdcs->rx_ring_alloc.vbase) {
1092 dma_pool_free(pdcs->ring_pool, pdcs->rx_ring_alloc.vbase,
1093 pdcs->rx_ring_alloc.dmabase);
1094 pdcs->rx_ring_alloc.vbase = NULL;
1118 * @pdcs: PDC state
1125 static bool pdc_rings_full(struct pdc_state *pdcs, int tx_cnt, int rx_cnt)
1132 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout,
1133 pdcs->nrxpost);
1135 pdcs->rx_ring_full++;
1140 tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout,
1141 pdcs->ntxpost);
1143 pdcs->tx_ring_full++;
1159 struct pdc_state *pdcs = chan->con_priv;
1162 if (unlikely(pdc_rings_full(pdcs, PDC_RING_SPACE_MIN,
1164 pdcs->last_tx_not_done++;
1196 struct pdc_state *pdcs = chan->con_priv;
1197 struct device *dev = &pdcs->pdev->dev;
1238 if (unlikely(pdc_rings_full(pdcs, tx_desc_req, rx_desc_req + 1)))
1242 err = pdc_rx_list_init(pdcs, mssg->spu.dst, mssg->ctx);
1243 err |= pdc_rx_list_sg_add(pdcs, mssg->spu.dst);
1246 err |= pdc_tx_list_sg_add(pdcs, mssg->spu.src);
1247 err |= pdc_tx_list_final(pdcs); /* initiate transfer */
1250 dev_err(&pdcs->pdev->dev,
1263 struct pdc_state *pdcs = chan->con_priv;
1265 if (!pdcs)
1268 dev_dbg(&pdcs->pdev->dev,
1269 "Shutdown mailbox channel for PDC %u", pdcs->pdc_idx);
1270 pdc_ring_free(pdcs);
1276 * @pdcs: state of the PDC
1279 void pdc_hw_init(struct pdc_state *pdcs)
1286 pdev = pdcs->pdev;
1289 dev_dbg(dev, "PDC %u initial values:", pdcs->pdc_idx);
1291 pdcs);
1293 pdcs->pdc_reg_vbase);
1296 pdcs->regs = (struct pdc_regs *)pdcs->pdc_reg_vbase;
1297 pdcs->txregs_64 = (struct dma64_regs *)
1298 (((u8 *)pdcs->pdc_reg_vbase) +
1300 pdcs->rxregs_64 = (struct dma64_regs *)
1301 (((u8 *)pdcs->pdc_reg_vbase) +
1304 pdcs->ntxd = PDC_RING_ENTRIES;
1305 pdcs->nrxd = PDC_RING_ENTRIES;
1306 pdcs->ntxpost = PDC_RING_ENTRIES - 1;
1307 pdcs->nrxpost = PDC_RING_ENTRIES - 1;
1308 iowrite32(0, &pdcs->regs->intmask);
1310 dma_reg = &pdcs->regs->dmaregs[ringset];
1315 iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1),
1322 if (pdcs->pdc_resp_hdr_len == PDC_SPU2_RESP_HDR_LEN)
1324 pdcs->pdc_reg_vbase + PDC_CKSUM_CTRL_OFFSET);
1329 * @pdcs: PDC state structure
1332 static void pdc_hw_disable(struct pdc_state *pdcs)
1336 dma_reg = &pdcs->regs->dmaregs[PDC_RINGSET];
1338 iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1),
1345 * @pdcs: PDC state structure
1353 static int pdc_rx_buf_pool_create(struct pdc_state *pdcs)
1358 pdev = pdcs->pdev;
1361 pdcs->pdc_resp_hdr_len = pdcs->rx_status_len;
1362 if (pdcs->use_bcm_hdr)
1363 pdcs->pdc_resp_hdr_len += BCM_HDR_LEN;
1365 pdcs->rx_buf_pool = dma_pool_create("pdc rx bufs", dev,
1366 pdcs->pdc_resp_hdr_len,
1368 if (!pdcs->rx_buf_pool)
1378 * @pdcs: PDC state
1386 static int pdc_interrupts_init(struct pdc_state *pdcs)
1388 struct platform_device *pdev = pdcs->pdev;
1394 iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET);
1396 if (pdcs->hw_type == FA_HW)
1397 iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase +
1400 iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase +
1404 pdcs->pdc_irq = irq_of_parse_and_map(dn, 0);
1405 dev_dbg(dev, "pdc device %s irq %u for pdcs %p",
1406 dev_name(dev), pdcs->pdc_irq, pdcs);
1408 err = devm_request_irq(dev, pdcs->pdc_irq, pdc_irq_handler, 0,
1412 pdcs->pdc_irq, err);
1427 * @pdcs: PDC state
1437 static int pdc_mb_init(struct pdc_state *pdcs)
1439 struct device *dev = &pdcs->pdev->dev;
1444 mbc = &pdcs->mbc;
1457 mbc->chans[chan_index].con_priv = pdcs;
1484 * @pdcs: PDC state
1493 static int pdc_dt_read(struct platform_device *pdev, struct pdc_state *pdcs)
1502 &pdcs->rx_status_len);
1508 pdcs->use_bcm_hdr = of_property_read_bool(dn, "brcm,use-bcm-hdr");
1510 pdcs->hw_type = PDC_HW;
1515 pdcs->hw_type = *hw_type;
1537 struct pdc_state *pdcs;
1540 pdcs = devm_kzalloc(dev, sizeof(*pdcs), GFP_KERNEL);
1541 if (!pdcs) {
1546 pdcs->pdev = pdev;
1547 platform_set_drvdata(pdev, pdcs);
1548 pdcs->pdc_idx = pdcg.num_spu;
1558 pdcs->ring_pool = dma_pool_create("pdc rings", dev, PDC_RING_SIZE,
1560 if (!pdcs->ring_pool) {
1565 err = pdc_dt_read(pdev, pdcs);
1577 pdcs->pdc_reg_vbase = devm_ioremap_resource(&pdev->dev, pdc_regs);
1578 if (IS_ERR(pdcs->pdc_reg_vbase)) {
1579 err = PTR_ERR(pdcs->pdc_reg_vbase);
1585 err = pdc_rx_buf_pool_create(pdcs);
1589 pdc_hw_init(pdcs);
1592 tasklet_setup(&pdcs->rx_tasklet, pdc_tasklet_cb);
1594 err = pdc_interrupts_init(pdcs);
1599 err = pdc_mb_init(pdcs);
1603 pdc_setup_debugfs(pdcs);
1609 tasklet_kill(&pdcs->rx_tasklet);
1610 dma_pool_destroy(pdcs->rx_buf_pool);
1613 dma_pool_destroy(pdcs->ring_pool);
1621 struct pdc_state *pdcs = platform_get_drvdata(pdev);
1625 tasklet_kill(&pdcs->rx_tasklet);
1627 pdc_hw_disable(pdcs);
1629 dma_pool_destroy(pdcs->rx_buf_pool);
1630 dma_pool_destroy(pdcs->ring_pool);