Lines Matching refs:reg
60 u32 reg;
62 reg = readl(mbox->base + RWTM_HOST_INT_RESET);
64 if (reg & SP_CMD_COMPLETE)
67 if (reg & (SP_CMD_QUEUE_FULL_ACCESS | SP_CMD_QUEUE_FULL))
70 writel(reg, mbox->base + RWTM_HOST_INT_RESET);
71 if (reg)
74 return reg ? IRQ_HANDLED : IRQ_NONE;
82 u32 reg;
87 reg = readl(mbox->base + RWTM_MBOX_FIFO_STATUS);
88 if (!(reg & FIFO_STS_RDY))
91 if ((reg & FIFO_STS_CNTR_MASK) >= FIFO_STS_CNTR_MAX) {
106 u32 reg;
117 reg = readl(mbox->base + RWTM_HOST_INT_MASK);
118 reg &= ~(SP_CMD_COMPLETE | SP_CMD_QUEUE_FULL_ACCESS | SP_CMD_QUEUE_FULL);
119 writel(reg, mbox->base + RWTM_HOST_INT_MASK);
126 u32 reg;
130 reg = readl(mbox->base + RWTM_HOST_INT_MASK);
131 reg |= SP_CMD_COMPLETE | SP_CMD_QUEUE_FULL_ACCESS | SP_CMD_QUEUE_FULL;
132 writel(reg, mbox->base + RWTM_HOST_INT_MASK);