Lines Matching refs:cdef
39 u8 channel; /* 1-based, max priv->cdef->channels */
44 const struct is31fl32xx_chipdef *cdef;
167 for (i = 0; i < priv->cdef->channels; i++) {
168 ret = is31fl32xx_write(priv, priv->cdef->pwm_register_base+i,
173 ret = is31fl32xx_write(priv, priv->cdef->pwm_update_reg, 0);
227 const struct is31fl32xx_chipdef *cdef = led_data->priv->cdef;
234 if (cdef->pwm_registers_reversed)
235 pwm_register_offset = cdef->channels - led_data->channel;
240 cdef->pwm_register_base + pwm_register_offset,
245 return is31fl32xx_write(led_data->priv, cdef->pwm_update_reg, 0);
250 const struct is31fl32xx_chipdef *cdef = priv->cdef;
253 if (cdef->reset_reg != IS31FL32XX_REG_NONE) {
254 ret = is31fl32xx_write(priv, cdef->reset_reg, 0);
259 if (cdef->reset_func)
260 return cdef->reset_func(priv);
268 const struct is31fl32xx_chipdef *cdef = priv->cdef;
271 if (cdef->shutdown_reg != IS31FL32XX_REG_NONE) {
274 ret = is31fl32xx_write(priv, cdef->shutdown_reg, value);
279 if (cdef->sw_shutdown_func)
280 return cdef->sw_shutdown_func(priv, enable);
287 const struct is31fl32xx_chipdef *cdef = priv->cdef;
298 if (cdef->led_control_register_base != IS31FL32XX_REG_NONE) {
300 GENMASK(cdef->enable_bits_per_led_control_register-1, 0);
301 u8 num_regs = cdef->channels /
302 cdef->enable_bits_per_led_control_register;
307 cdef->led_control_register_base+i,
318 if (cdef->global_control_reg != IS31FL32XX_REG_NONE) {
319 ret = is31fl32xx_write(priv, cdef->global_control_reg, 0x00);
336 if (ret || reg < 1 || reg > led_data->priv->cdef->channels) {
427 const struct is31fl32xx_chipdef *cdef;
433 cdef = device_get_match_data(dev);
445 priv->cdef = cdef;