Lines Matching refs:hw
267 struct inf_hw *hw = dev_id;
270 spin_lock(&hw->lock);
271 val = inb((u32)hw->cfg.start + DIVA_PCI_CTRL);
273 spin_unlock(&hw->lock);
276 hw->irqcnt++;
277 mISDNipac_irq(&hw->ipac, irqloops);
278 spin_unlock(&hw->lock);
285 struct inf_hw *hw = dev_id;
288 spin_lock(&hw->lock);
289 val = readb(hw->cfg.p);
291 spin_unlock(&hw->lock);
294 hw->irqcnt++;
295 mISDNipac_irq(&hw->ipac, irqloops);
296 writeb(PITA_INT0_STATUS, hw->cfg.p); /* ACK PITA INT0 */
297 spin_unlock(&hw->lock);
304 struct inf_hw *hw = dev_id;
307 spin_lock(&hw->lock);
308 val = inb((u32)hw->cfg.start + TIGER_AUX_STATUS);
310 spin_unlock(&hw->lock);
313 hw->irqcnt++;
314 mISDNipac_irq(&hw->ipac, irqloops);
315 spin_unlock(&hw->lock);
322 struct inf_hw *hw = dev_id;
325 spin_lock(&hw->lock);
326 val = inb((u32)hw->cfg.start + ELSA_IRQ_ADDR);
328 spin_unlock(&hw->lock);
331 hw->irqcnt++;
332 mISDNipac_irq(&hw->ipac, irqloops);
333 spin_unlock(&hw->lock);
340 struct inf_hw *hw = dev_id;
343 spin_lock(&hw->lock);
344 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
346 spin_unlock(&hw->lock);
349 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
350 hw->irqcnt++;
351 mISDNipac_irq(&hw->ipac, irqloops);
352 spin_unlock(&hw->lock);
359 struct inf_hw *hw = dev_id;
362 spin_lock(&hw->lock);
363 ret = mISDNipac_irq(&hw->ipac, irqloops);
364 spin_unlock(&hw->lock);
371 struct inf_hw *hw = dev_id;
374 spin_lock(&hw->lock);
375 val = hw->ipac.read_reg(hw, IPAC_ISTA);
377 spin_unlock(&hw->lock);
380 hw->irqcnt++;
381 mISDNipac_irq(&hw->ipac, irqloops);
382 spin_unlock(&hw->lock);
387 enable_hwirq(struct inf_hw *hw)
392 switch (hw->ci->typ) {
395 writel(PITA_INT0_ENABLE, hw->cfg.p);
399 outb(TIGER_IRQ_BIT, (u32)hw->cfg.start + TIGER_AUX_IRQMASK);
402 outb(QS1000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
405 outb(QS3000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
408 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
410 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
413 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
415 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
419 (u32)hw->cfg.start + GAZEL_INCSR);
423 (u32)hw->cfg.start + GAZEL_INCSR);
431 disable_hwirq(struct inf_hw *hw)
436 switch (hw->ci->typ) {
439 writel(0, hw->cfg.p);
443 outb(0, (u32)hw->cfg.start + TIGER_AUX_IRQMASK);
446 outb(QS1000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
449 outb(QS3000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
452 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
454 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
457 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
459 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
463 outb(0, (u32)hw->cfg.start + GAZEL_INCSR);
471 ipac_chip_reset(struct inf_hw *hw)
473 hw->ipac.write_reg(hw, IPAC_POTA2, 0x20);
475 hw->ipac.write_reg(hw, IPAC_POTA2, 0x00);
477 hw->ipac.write_reg(hw, IPAC_CONF, hw->ipac.conf);
478 hw->ipac.write_reg(hw, IPAC_MASK, 0xc0);
482 reset_inf(struct inf_hw *hw)
488 pr_notice("%s: resetting card\n", hw->name);
489 switch (hw->ci->typ) {
492 outb(0, (u32)hw->cfg.start + DIVA_PCI_CTRL);
494 outb(DIVA_RESET_BIT, (u32)hw->cfg.start + DIVA_PCI_CTRL);
497 outb(9, (u32)hw->cfg.start + 0x69);
499 (u32)hw->cfg.start + DIVA_PCI_CTRL);
503 hw->cfg.p + PITA_MISC_REG);
505 writel(PITA_PARA_MPX_MODE, hw->cfg.p + PITA_MISC_REG);
510 hw->cfg.p + PITA_MISC_REG);
513 hw->cfg.p + PITA_MISC_REG);
518 ipac_chip_reset(hw);
519 hw->ipac.write_reg(hw, IPAC_ACFG, 0xff);
520 hw->ipac.write_reg(hw, IPAC_AOE, 0x00);
521 hw->ipac.write_reg(hw, IPAC_PCFG, 0x12);
525 ipac_chip_reset(hw);
526 hw->ipac.write_reg(hw, IPAC_ACFG, 0x00);
527 hw->ipac.write_reg(hw, IPAC_AOE, 0x3c);
528 hw->ipac.write_reg(hw, IPAC_ATX, 0xff);
533 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
535 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
537 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
539 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
543 val = inl((u32)hw->cfg.start + GAZEL_CNTRL);
545 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
548 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
550 hw->ipac.isac.adf2 = 0x87;
551 hw->ipac.hscx[0].slot = 0x1f;
552 hw->ipac.hscx[1].slot = 0x23;
555 val = inl((u32)hw->cfg.start + GAZEL_CNTRL);
557 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
560 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
562 ipac_chip_reset(hw);
563 hw->ipac.write_reg(hw, IPAC_ACFG, 0xff);
564 hw->ipac.write_reg(hw, IPAC_AOE, 0x00);
565 hw->ipac.conf = 0x01; /* IOM off */
570 enable_hwirq(hw);
574 inf_ctrl(struct inf_hw *hw, u32 cmd, u_long arg)
580 reset_inf(hw);
584 hw->name, __func__, cmd, arg);
592 init_irq(struct inf_hw *hw)
597 if (!hw->ci->irqfunc)
599 ret = request_irq(hw->irq, hw->ci->irqfunc, IRQF_SHARED, hw->name, hw);
601 pr_info("%s: couldn't get interrupt %d\n", hw->name, hw->irq);
605 spin_lock_irqsave(&hw->lock, flags);
606 reset_inf(hw);
607 ret = hw->ipac.init(&hw->ipac);
609 spin_unlock_irqrestore(&hw->lock, flags);
611 hw->name, ret);
614 spin_unlock_irqrestore(&hw->lock, flags);
617 pr_notice("%s: IRQ %d count %d\n", hw->name,
618 hw->irq, hw->irqcnt);
619 if (!hw->irqcnt) {
621 hw->name, hw->irq, 3 - cnt);
625 free_irq(hw->irq, hw);
630 release_io(struct inf_hw *hw)
632 if (hw->cfg.mode) {
633 if (hw->cfg.mode == AM_MEMIO) {
634 release_mem_region(hw->cfg.start, hw->cfg.size);
635 if (hw->cfg.p)
636 iounmap(hw->cfg.p);
638 release_region(hw->cfg.start, hw->cfg.size);
639 hw->cfg.mode = AM_NONE;
641 if (hw->addr.mode) {
642 if (hw->addr.mode == AM_MEMIO) {
643 release_mem_region(hw->addr.start, hw->addr.size);
644 if (hw->addr.p)
645 iounmap(hw->addr.p);
647 release_region(hw->addr.start, hw->addr.size);
648 hw->addr.mode = AM_NONE;
653 setup_io(struct inf_hw *hw)
657 if (hw->ci->cfg_mode) {
658 hw->cfg.start = pci_resource_start(hw->pdev, hw->ci->cfg_bar);
659 hw->cfg.size = pci_resource_len(hw->pdev, hw->ci->cfg_bar);
660 if (hw->ci->cfg_mode == AM_MEMIO) {
661 if (!request_mem_region(hw->cfg.start, hw->cfg.size,
662 hw->name))
665 if (!request_region(hw->cfg.start, hw->cfg.size,
666 hw->name))
671 "already in use\n", hw->name,
672 (ulong)hw->cfg.start, (ulong)hw->cfg.size);
675 hw->cfg.mode = hw->ci->cfg_mode;
676 if (hw->ci->cfg_mode == AM_MEMIO) {
677 hw->cfg.p = ioremap(hw->cfg.start, hw->cfg.size);
678 if (!hw->cfg.p)
683 hw->name, (ulong)hw->cfg.start,
684 (ulong)hw->cfg.size, hw->ci->cfg_mode);
687 if (hw->ci->addr_mode) {
688 hw->addr.start = pci_resource_start(hw->pdev, hw->ci->addr_bar);
689 hw->addr.size = pci_resource_len(hw->pdev, hw->ci->addr_bar);
690 if (hw->ci->addr_mode == AM_MEMIO) {
691 if (!request_mem_region(hw->addr.start, hw->addr.size,
692 hw->name))
695 if (!request_region(hw->addr.start, hw->addr.size,
696 hw->name))
701 "already in use\n", hw->name,
702 (ulong)hw->addr.start, (ulong)hw->addr.size);
705 hw->addr.mode = hw->ci->addr_mode;
706 if (hw->ci->addr_mode == AM_MEMIO) {
707 hw->addr.p = ioremap(hw->addr.start, hw->addr.size);
708 if (!hw->addr.p)
713 hw->name, (ulong)hw->addr.start,
714 (ulong)hw->addr.size, hw->ci->addr_mode);
718 switch (hw->ci->typ) {
721 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX;
722 hw->isac.mode = hw->cfg.mode;
723 hw->isac.a.io.ale = (u32)hw->cfg.start + DIVA_ISAC_ALE;
724 hw->isac.a.io.port = (u32)hw->cfg.start + DIVA_ISAC_PORT;
725 hw->hscx.mode = hw->cfg.mode;
726 hw->hscx.a.io.ale = (u32)hw->cfg.start + DIVA_HSCX_ALE;
727 hw->hscx.a.io.port = (u32)hw->cfg.start + DIVA_HSCX_PORT;
730 hw->ipac.type = IPAC_TYPE_IPAC;
731 hw->ipac.isac.off = 0x80;
732 hw->isac.mode = hw->addr.mode;
733 hw->isac.a.p = hw->addr.p;
734 hw->hscx.mode = hw->addr.mode;
735 hw->hscx.a.p = hw->addr.p;
738 hw->ipac.type = IPAC_TYPE_IPACX;
739 hw->isac.mode = hw->addr.mode;
740 hw->isac.a.p = hw->addr.p;
741 hw->hscx.mode = hw->addr.mode;
742 hw->hscx.a.p = hw->addr.p;
746 hw->ipac.type = IPAC_TYPE_IPAC;
747 hw->ipac.isac.off = 0x80;
748 hw->isac.mode = hw->cfg.mode;
749 hw->isac.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE;
750 hw->isac.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT;
751 hw->hscx.mode = hw->cfg.mode;
752 hw->hscx.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE;
753 hw->hscx.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT;
754 outb(0xff, (ulong)hw->cfg.start);
756 outb(0x00, (ulong)hw->cfg.start);
758 outb(TIGER_IOMASK, (ulong)hw->cfg.start + TIGER_AUX_CTRL);
762 hw->ipac.type = IPAC_TYPE_IPAC;
763 hw->ipac.isac.off = 0x80;
764 hw->isac.a.io.ale = (u32)hw->addr.start;
765 hw->isac.a.io.port = (u32)hw->addr.start + 1;
766 hw->isac.mode = hw->addr.mode;
767 hw->hscx.a.io.ale = (u32)hw->addr.start;
768 hw->hscx.a.io.port = (u32)hw->addr.start + 1;
769 hw->hscx.mode = hw->addr.mode;
772 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX;
773 hw->isac.mode = hw->addr.mode;
774 hw->isac.a.io.ale = (u32)hw->addr.start + NICCY_ISAC_ALE;
775 hw->isac.a.io.port = (u32)hw->addr.start + NICCY_ISAC_PORT;
776 hw->hscx.mode = hw->addr.mode;
777 hw->hscx.a.io.ale = (u32)hw->addr.start + NICCY_HSCX_ALE;
778 hw->hscx.a.io.port = (u32)hw->addr.start + NICCY_HSCX_PORT;
781 hw->ipac.type = IPAC_TYPE_IPAC;
782 hw->ipac.isac.off = 0x80;
783 hw->isac.a.io.ale = (u32)hw->addr.start;
784 hw->isac.a.io.port = hw->isac.a.io.ale + 4;
785 hw->isac.mode = hw->addr.mode;
786 hw->hscx.a.io.ale = hw->isac.a.io.ale;
787 hw->hscx.a.io.port = hw->isac.a.io.port;
788 hw->hscx.mode = hw->addr.mode;
791 hw->ipac.type = IPAC_TYPE_IPAC;
792 hw->ipac.isac.off = 0x80;
793 hw->isac.a.io.ale = (u32)hw->addr.start + 0x08;
794 hw->isac.a.io.port = hw->isac.a.io.ale + 4;
795 hw->isac.mode = hw->addr.mode;
796 hw->hscx.a.io.ale = hw->isac.a.io.ale;
797 hw->hscx.a.io.port = hw->isac.a.io.port;
798 hw->hscx.mode = hw->addr.mode;
801 hw->ipac.type = IPAC_TYPE_IPAC;
802 hw->ipac.isac.off = 0x80;
803 hw->isac.a.io.ale = (u32)hw->addr.start + 0x10;
804 hw->isac.a.io.port = hw->isac.a.io.ale + 4;
805 hw->isac.mode = hw->addr.mode;
806 hw->hscx.a.io.ale = hw->isac.a.io.ale;
807 hw->hscx.a.io.port = hw->isac.a.io.port;
808 hw->hscx.mode = hw->addr.mode;
811 hw->ipac.type = IPAC_TYPE_IPAC;
812 hw->ipac.isac.off = 0x80;
813 hw->isac.a.io.ale = (u32)hw->addr.start + 0x20;
814 hw->isac.a.io.port = hw->isac.a.io.ale + 4;
815 hw->isac.mode = hw->addr.mode;
816 hw->hscx.a.io.ale = hw->isac.a.io.ale;
817 hw->hscx.a.io.port = hw->isac.a.io.port;
818 hw->hscx.mode = hw->addr.mode;
821 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX;
822 hw->ipac.isac.off = 0x80;
823 hw->isac.mode = hw->addr.mode;
824 hw->isac.a.io.port = (u32)hw->addr.start;
825 hw->hscx.mode = hw->addr.mode;
826 hw->hscx.a.io.port = hw->isac.a.io.port;
829 hw->ipac.type = IPAC_TYPE_IPAC;
830 hw->ipac.isac.off = 0x80;
831 hw->isac.mode = hw->addr.mode;
832 hw->isac.a.io.ale = (u32)hw->addr.start;
833 hw->isac.a.io.port = (u32)hw->addr.start + GAZEL_IPAC_DATA_PORT;
834 hw->hscx.mode = hw->addr.mode;
835 hw->hscx.a.io.ale = hw->isac.a.io.ale;
836 hw->hscx.a.io.port = hw->isac.a.io.port;
841 switch (hw->isac.mode) {
843 ASSIGN_FUNC_IPAC(MIO, hw->ipac);
846 ASSIGN_FUNC_IPAC(IND, hw->ipac);
849 ASSIGN_FUNC_IPAC(IO, hw->ipac);