Lines Matching defs:ictlr
62 { .compatible = "nvidia,tegra210-ictlr", .data = &tegra210_ictlr_soc },
63 { .compatible = "nvidia,tegra30-ictlr", .data = &tegra30_ictlr_soc },
64 { .compatible = "nvidia,tegra20-ictlr", .data = &tegra20_ictlr_soc },
142 void __iomem *ictlr = lic->base[i];
145 lic->cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
146 lic->cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
147 lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
148 lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
151 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);
154 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);
156 /* Enable the wakeup sources of ictlr */
157 writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
171 void __iomem *ictlr = lic->base[i];
174 ictlr + ICTLR_CPU_IEP_CLASS);
175 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);
177 ictlr + ICTLR_CPU_IER_SET);
179 ictlr + ICTLR_COP_IEP_CLASS);
180 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);
182 ictlr + ICTLR_COP_IER_SET);
256 int ictlr = (hwirq + i) / 32;
260 (void __force *)info->base[ictlr]);
357 IRQCHIP_DECLARE(tegra20_ictlr, "nvidia,tegra20-ictlr", tegra_ictlr_init);
358 IRQCHIP_DECLARE(tegra30_ictlr, "nvidia,tegra30-ictlr", tegra_ictlr_init);
359 IRQCHIP_DECLARE(tegra210_ictlr, "nvidia,tegra210-ictlr", tegra_ictlr_init);