Lines Matching refs:sei
3 #define pr_fmt(fmt) "mvebu-sei: " fmt
58 struct mvebu_sei *sei = irq_data_get_irq_chip_data(d);
62 sei->base + GICP_SECR(reg_idx));
67 struct mvebu_sei *sei = irq_data_get_irq_chip_data(d);
72 raw_spin_lock_irqsave(&sei->mask_lock, flags);
73 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx));
75 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx));
76 raw_spin_unlock_irqrestore(&sei->mask_lock, flags);
81 struct mvebu_sei *sei = irq_data_get_irq_chip_data(d);
86 raw_spin_lock_irqsave(&sei->mask_lock, flags);
87 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx));
89 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx));
90 raw_spin_unlock_irqrestore(&sei->mask_lock, flags);
141 struct mvebu_sei *sei = data->chip_data;
142 phys_addr_t set = sei->res->start + GICP_SET_SEI_OFFSET;
144 msg->data = data->hwirq + sei->caps->cp_range.first;
170 struct mvebu_sei *sei = domain->host_data;
175 &mvebu_sei_irq_chip, sei);
211 struct mvebu_sei *sei = domain->host_data;
221 fwspec.param[0] = hwirq + sei->caps->ap_range.first;
228 &mvebu_sei_ap_irq_chip, sei,
241 static void mvebu_sei_cp_release_irq(struct mvebu_sei *sei, unsigned long hwirq)
243 mutex_lock(&sei->cp_msi_lock);
244 clear_bit(hwirq, sei->cp_msi_bitmap);
245 mutex_unlock(&sei->cp_msi_lock);
252 struct mvebu_sei *sei = domain->host_data;
261 mutex_lock(&sei->cp_msi_lock);
262 hwirq = find_first_zero_bit(sei->cp_msi_bitmap,
263 sei->caps->cp_range.size);
264 if (hwirq < sei->caps->cp_range.size)
265 set_bit(hwirq, sei->cp_msi_bitmap);
266 mutex_unlock(&sei->cp_msi_lock);
268 if (hwirq == sei->caps->cp_range.size)
273 fwspec.param[0] = hwirq + sei->caps->cp_range.first;
280 &mvebu_sei_cp_irq_chip, sei,
286 mvebu_sei_cp_release_irq(sei, hwirq);
293 struct mvebu_sei *sei = domain->host_data;
296 if (nr_irqs != 1 || d->hwirq >= sei->caps->cp_range.size) {
297 dev_err(sei->dev, "Invalid hwirq %lu\n", d->hwirq);
301 mvebu_sei_cp_release_irq(sei, d->hwirq);
327 struct mvebu_sei *sei = irq_desc_get_handler_data(desc);
337 irqmap = readl_relaxed(sei->base + GICP_SECR(idx));
343 virq = irq_find_mapping(sei->sei_domain, hwirq);
349 dev_warn(sei->dev,
357 static void mvebu_sei_reset(struct mvebu_sei *sei)
363 writel_relaxed(0xFFFFFFFF, sei->base + GICP_SECR(reg_idx));
364 writel_relaxed(0xFFFFFFFF, sei->base + GICP_SEMR(reg_idx));
372 struct mvebu_sei *sei;
376 sei = devm_kzalloc(&pdev->dev, sizeof(*sei), GFP_KERNEL);
377 if (!sei)
380 sei->dev = &pdev->dev;
382 mutex_init(&sei->cp_msi_lock);
383 raw_spin_lock_init(&sei->mask_lock);
385 sei->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
386 sei->base = devm_ioremap_resource(sei->dev, sei->res);
387 if (IS_ERR(sei->base)) {
388 dev_err(sei->dev, "Failed to remap SEI resource\n");
389 return PTR_ERR(sei->base);
393 sei->caps = of_device_get_match_data(&pdev->dev);
394 if (!sei->caps) {
395 dev_err(sei->dev,
406 dev_err(sei->dev, "Failed to retrieve top-level SPI IRQ\n");
411 sei->sei_domain = irq_domain_create_linear(of_node_to_fwnode(node),
412 (sei->caps->ap_range.size +
413 sei->caps->cp_range.size),
415 sei);
416 if (!sei->sei_domain) {
417 dev_err(sei->dev, "Failed to create SEI IRQ domain\n");
422 irq_domain_update_bus_token(sei->sei_domain, DOMAIN_BUS_NEXUS);
425 sei->ap_domain = irq_domain_create_hierarchy(sei->sei_domain, 0,
426 sei->caps->ap_range.size,
429 sei);
430 if (!sei->ap_domain) {
431 dev_err(sei->dev, "Failed to create AP IRQ domain\n");
436 irq_domain_update_bus_token(sei->ap_domain, DOMAIN_BUS_WIRED);
439 sei->cp_domain = irq_domain_create_hierarchy(sei->sei_domain, 0,
440 sei->caps->cp_range.size,
443 sei);
444 if (!sei->cp_domain) {
450 irq_domain_update_bus_token(sei->cp_domain, DOMAIN_BUS_GENERIC_MSI);
454 sei->cp_domain);
461 mvebu_sei_reset(sei);
465 sei);
470 irq_domain_remove(sei->cp_domain);
472 irq_domain_remove(sei->ap_domain);
474 irq_domain_remove(sei->sei_domain);
494 .compatible = "marvell,ap806-sei",
503 .name = "mvebu-sei",