Lines Matching refs:pic
35 static void mvebu_pic_reset(struct mvebu_pic *pic)
38 writel(0, pic->base + PIC_MASK);
39 writel(PIC_MAX_IRQ_MASK, pic->base + PIC_CAUSE);
44 struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);
46 writel(1 << d->hwirq, pic->base + PIC_CAUSE);
51 struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);
54 reg = readl(pic->base + PIC_MASK);
56 writel(reg, pic->base + PIC_MASK);
61 struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);
64 reg = readl(pic->base + PIC_MASK);
66 writel(reg, pic->base + PIC_MASK);
72 struct mvebu_pic *pic = domain->host_data;
75 irq_set_chip_data(virq, pic);
76 irq_set_chip_and_handler(virq, &pic->irq_chip,
91 struct mvebu_pic *pic = irq_desc_get_handler_data(desc);
96 irqmap = readl_relaxed(pic->base + PIC_CAUSE);
100 cascade_irq = irq_find_mapping(pic->domain, irqn);
109 struct mvebu_pic *pic = data;
111 mvebu_pic_reset(pic);
112 enable_percpu_irq(pic->parent_irq, IRQ_TYPE_NONE);
117 struct mvebu_pic *pic = data;
119 disable_percpu_irq(pic->parent_irq);
125 struct mvebu_pic *pic;
129 pic = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pic), GFP_KERNEL);
130 if (!pic)
134 pic->base = devm_ioremap_resource(&pdev->dev, res);
135 if (IS_ERR(pic->base))
136 return PTR_ERR(pic->base);
138 irq_chip = &pic->irq_chip;
144 pic->parent_irq = irq_of_parse_and_map(node, 0);
145 if (pic->parent_irq <= 0) {
150 pic->domain = irq_domain_add_linear(node, PIC_MAX_IRQS,
151 &mvebu_pic_domain_ops, pic);
152 if (!pic->domain) {
157 irq_set_chained_handler(pic->parent_irq, mvebu_pic_handle_cascade_irq);
158 irq_set_handler_data(pic->parent_irq, pic);
160 on_each_cpu(mvebu_pic_enable_percpu_irq, pic, 1);
162 platform_set_drvdata(pdev, pic);
169 struct mvebu_pic *pic = platform_get_drvdata(pdev);
171 on_each_cpu(mvebu_pic_disable_percpu_irq, pic, 1);
172 irq_domain_remove(pic->domain);
178 { .compatible = "marvell,armada-8k-pic", },
187 .name = "mvebu-pic",