Lines Matching defs:icu_data
62 static struct icu_chip_data icu_data[MAX_ICU_NR];
75 if (data == &icu_data[0]) {
99 if (data == &icu_data[0]) {
128 if (data == &icu_data[0]) {
158 if (irq == icu_data[i].cascade_irq) {
159 domain = icu_data[i].domain;
175 generic_handle_irq(icu_data[i].virq_base + n);
233 handle_domain_irq(icu_data[0].domain, hwirq, regs);
244 handle_domain_irq(icu_data[0].domain, hwirq, regs);
254 icu_data[0].conf_enable = mmp_conf.conf_enable;
255 icu_data[0].conf_disable = mmp_conf.conf_disable;
256 icu_data[0].conf_mask = mmp_conf.conf_mask;
257 icu_data[0].nr_irqs = 64;
258 icu_data[0].virq_base = 0;
259 icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
261 &icu_data[0]);
266 irq_set_default_host(icu_data[0].domain);
277 icu_data[0].conf_enable = mmp2_conf.conf_enable;
278 icu_data[0].conf_disable = mmp2_conf.conf_disable;
279 icu_data[0].conf_mask = mmp2_conf.conf_mask;
280 icu_data[0].nr_irqs = 64;
281 icu_data[0].virq_base = 0;
282 icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
284 &icu_data[0]);
285 icu_data[1].reg_status = mmp_icu_base + 0x150;
286 icu_data[1].reg_mask = mmp_icu_base + 0x168;
287 icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base +
288 icu_data[0].nr_irqs;
289 icu_data[1].clr_mfp_hwirq = 1; /* offset to IRQ_MMP2_PMIC_BASE */
290 icu_data[1].nr_irqs = 2;
291 icu_data[1].cascade_irq = 4;
292 icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs;
293 icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
294 icu_data[1].virq_base, 0,
296 &icu_data[1]);
297 icu_data[2].reg_status = mmp_icu_base + 0x154;
298 icu_data[2].reg_mask = mmp_icu_base + 0x16c;
299 icu_data[2].nr_irqs = 2;
300 icu_data[2].cascade_irq = 5;
301 icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs;
302 icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
303 icu_data[2].virq_base, 0,
305 &icu_data[2]);
306 icu_data[3].reg_status = mmp_icu_base + 0x180;
307 icu_data[3].reg_mask = mmp_icu_base + 0x17c;
308 icu_data[3].nr_irqs = 3;
309 icu_data[3].cascade_irq = 9;
310 icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs;
311 icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
312 icu_data[3].virq_base, 0,
314 &icu_data[3]);
315 icu_data[4].reg_status = mmp_icu_base + 0x158;
316 icu_data[4].reg_mask = mmp_icu_base + 0x170;
317 icu_data[4].nr_irqs = 5;
318 icu_data[4].cascade_irq = 17;
319 icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs;
320 icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
321 icu_data[4].virq_base, 0,
323 &icu_data[4]);
324 icu_data[5].reg_status = mmp_icu_base + 0x15c;
325 icu_data[5].reg_mask = mmp_icu_base + 0x174;
326 icu_data[5].nr_irqs = 15;
327 icu_data[5].cascade_irq = 35;
328 icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs;
329 icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
330 icu_data[5].virq_base, 0,
332 &icu_data[5]);
333 icu_data[6].reg_status = mmp_icu_base + 0x160;
334 icu_data[6].reg_mask = mmp_icu_base + 0x178;
335 icu_data[6].nr_irqs = 2;
336 icu_data[6].cascade_irq = 51;
337 icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs;
338 icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
339 icu_data[6].virq_base, 0,
341 &icu_data[6]);
342 icu_data[7].reg_status = mmp_icu_base + 0x188;
343 icu_data[7].reg_mask = mmp_icu_base + 0x184;
344 icu_data[7].nr_irqs = 2;
345 icu_data[7].cascade_irq = 55;
346 icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs;
347 icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
348 icu_data[7].virq_base, 0,
350 &icu_data[7]);
351 end = icu_data[7].virq_base + icu_data[7].nr_irqs;
354 if (irq == icu_data[1].cascade_irq ||
355 irq == icu_data[2].cascade_irq ||
356 irq == icu_data[3].cascade_irq ||
357 irq == icu_data[4].cascade_irq ||
358 irq == icu_data[5].cascade_irq ||
359 irq == icu_data[6].cascade_irq ||
360 irq == icu_data[7].cascade_irq) {
368 irq_set_default_host(icu_data[0].domain);
389 icu_data[0].virq_base = 0;
390 icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,
392 &icu_data[0]);
394 ret = irq_create_mapping(icu_data[0].domain, irq);
400 icu_data[0].virq_base = ret;
402 icu_data[0].nr_irqs = nr_irqs;
405 if (icu_data[0].virq_base) {
407 irq_dispose_mapping(icu_data[0].virq_base + i);
409 irq_domain_remove(icu_data[0].domain);
423 icu_data[0].conf_enable = mmp_conf.conf_enable;
424 icu_data[0].conf_disable = mmp_conf.conf_disable;
425 icu_data[0].conf_mask = mmp_conf.conf_mask;
441 icu_data[0].conf_enable = mmp2_conf.conf_enable;
442 icu_data[0].conf_disable = mmp2_conf.conf_disable;
443 icu_data[0].conf_mask = mmp2_conf.conf_mask;
467 icu_data[0].conf_enable = mmp3_conf.conf_enable;
468 icu_data[0].conf_disable = mmp3_conf.conf_disable;
469 icu_data[0].conf_mask = mmp3_conf.conf_mask;
470 icu_data[0].conf2_mask = mmp3_conf.conf2_mask;
513 icu_data[i].reg_status = mmp_icu_base + reg[0];
514 icu_data[i].reg_mask = mmp_icu_base + reg[2];
515 icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
516 if (!icu_data[i].cascade_irq)
519 icu_data[i].virq_base = 0;
520 icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,
522 &icu_data[i]);
524 ret = irq_create_mapping(icu_data[i].domain, irq);
530 icu_data[i].virq_base = ret;
532 icu_data[i].nr_irqs = nr_irqs;
535 icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;
536 icu_data[i].clr_mfp_hwirq = mfp_irq;
538 irq_set_chained_handler(icu_data[i].cascade_irq,
543 if (icu_data[i].virq_base) {
545 irq_dispose_mapping(icu_data[i].virq_base + j);
547 irq_domain_remove(icu_data[i].domain);